Graf Elektronik FLO3 Handbuch Seite 45

PINOUTS
PIN
NUMBER
1
19
20
21
40
PIN NAME
NOCONNECTION
MASTER RESET
POWER SUPPLI ES
COMPUTER INTERFACE:
2
3
4
5,6
7-14
24
38
39
WRITE ENABLE
CHIPSELECT
REAO ENABLE
REGISTER SELECT LINES
DATA ACCESS LINES
CLOCK
DATA REQUEST
INTERRUPT REQUEST
FLOPPY DISK INTERFACE:
15
16
17
18
STEP
D1RECTION
EARLY
LATE
SYMBOL
NC
MR
Vss
Vcc
Voo
WE
es
RE
A0.A1
DAL0-DAL7
CLK
DRQ
INTRQ
STEP
DIRC
EARLY
LATE
FUNCTION
Pin 1 is internally connected to a back blas generator and
must be lef t open by tha user.
A logic Iow (50 microseconds min.) on this input resets the
device and loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE. When RR is
brought to a logic high a RESTORE Command Is executed,
regardless of ths State or the Ready Signal from the drive.
Also, HEX 01 is loaded Into sector register.
Ground
+ 5V±5%
+ 12V*5%
A logic Iow on this input gates data on the DAL into the
selected register when 65 is Iow.
A logic Iow on this input selects the Chip and enables
Computer communication wlth ths device.
A logic Iow on this input controls theplacement of data from a
selected register on the DAL when CS Is Iow.
These inputs select the register to recelveftransfer data on the
DAL lines under RE and Wl control:
ÖS A1 A0 Rt WE
0 0 0 Status Reg Command Reg
0 0 1 Track Reg Track Reg
0 1 0 Sector Rag Sector Reg
0 1 1 Data Reg Data Reg
Eight bit Bidirectlonal bus used for transfer of data, control,
and Status. This bus is receiver enabled by WE" or transmltter
enabled by RE. Each line will drlve 1 Standard TTL load.
This input requires a free-runnlng 50% duty cycle Square wave
dock for Intemal Ilming reference, 2 MHz ± 1% for 8" drlves,
1 MHz ±1% forminMloppl8S.
This open draln Output indicates that the DR contains
assembled data in Read operations, or the DR is empty In
Writs operations. This Signal is reset when serviced by the
Computer through reading or loadlng the DR in Read or Write
operations, respectively. Use 10K pull-up resistor to + 5.
This open draln Output is set at the comptetion of any com
mand and Is reset when the STATUS register is read or the
command register is written to. Use 10K pull-up resistor to
+5.
The step Output contains a pulse for each step.
Direction Output is active high when stepping in, active Iow
when stepplng out.
Indicates that tha WRITE DATA pulse oecuring while Eariy is
active (high) should be shlfted eariy for wrlte preconv
pensation.
Indicates that the wrlte data pulse oeeunring whlle Laie is
active (high) should be shlfted late for write precompensation.
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