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Graf Elektronik FLO3 Handbuch Seite 51

Der fioppy-controller für den ndr-computer und den sb-computer
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TYPE I COMMANDS
Tha Type I Command3 Includo the Reslore, Seek, Slep,
Siep-In, and Slep-Out commands. Each of the Type I
Commands contalns a ralo lield (r0 M), which determines
theslepplng motor ralo as dotinocl inTable3.
A 2>is(MFM) or 4|is(FM| pulse is provided asan outpul lo
the drive, For every slop pulse issued, the drive moves one
track locatlon In a directlon delermined by the direclion
outpul. The Chip will step the dnve in Ihe same direction it
last aleppod unless Ihe command changes the direction.
The Direction Signal Is active high when stepping in and
tow when stepping out. The Direction Signal is valid 12 us
before the lirst slepping pulse is generated.
The rates (shown in Table 3) can be applied to a Step-
DiFectton Motor thiough Ihe device interface.
TABLE 3. STEPPING RATES
CLK
ÖDEM
Rl RO
0
0
0
1
1
0
1
1
7 MHl
0
TESTM
3 ms
6 ms
10 ms
IS™
1
TEST-I
3 ms
6 ms
10 rns
-5 m,
1 MHi
0
TEST-1
6rr-S
1!ms
Wm,
30 ms
1 MHl
I
TEST'1
6 ms
1? ms
30 ms
3U ms
«
TEST=O
ia*.»5
IMus
1 MH;
«
TEST=O
368,:S
396^s
After the last dircctional step an additional 15 milliseccnds
o( head settllng time lakes place if the Verify flag is sei in
Type I commands. Note that Ihis time doubles lo 30 ms lor
a 1 MHz dock. If TEST a 0, tliere is zero settling time.
There is also a 15 ms head settling time il ihe E Nag issel in
anyTypellor Hl command.
When a Seak, Step or Fiestore command is executed an
oplional verification of Read-Write head Position can be
performed by settling bil 2|V = 1) in the command word to
alogic 1. Theverilicalion Operation begins at ihe end oi the
15millisecond settling time afler the head is loaded against
the media. The track number Irom ihe ürst encountered ID
Field Is compared against the Contents ol Ihe Track
Register. l( Ihe Irack numbers compare and Ihe ID Field
Cyclic Hedundancy Check (CRC) is correct, the venfy
Operation is complete and an INTRQ is generated wilh no
errors. II there is a match but nol a valid CRC, Ihe CRC error
stalus bit is set (Slalus bit 3), and Ihe next encountered ID
field isreatt Irom Ihe disk for the veriticalion Operation.
The FD179X must find an !D tield with correct track number
and conect CRC within 5
revolutions
of
Ihe media
otherwlse the seek error is set and an INTRO is generated.
IIV = 0, no verification is performed.
The Head Load (HLO) Output controls Ihe movemenl ol the
readiwrite head againsl the modia. HLD is activated at the
beginnlng of aTypel command if the h flag isset (h = 1}, at
the end of Ihe Type I commanci if Ihe verify Nag (V a 1), or
upon receipt of any Type II or III command, Once HLD is
active it remains active until either a Type I command is
received with (h = 0 and V = 0); or if the FD179X is in an
idle State(non'busy]and 15index pulses have occurred.
Head Load timing (HLT) is an input to the FD179X which is
used lor the head engagu time. When HLT = 1, ihe FD179X
assumes
ihe
head
is campielely
engaged.
The
head
engage timi: is typically 30 to 100 ms depending on drive.
The Iow to tiigh iransition on HLD is lypically used to [trg a
one shot. The oulput ol the one shot is then used for HLT
and supplied as an input lo the FD179X.
HLt>[
'
J
1
ir
'""■"
'
HEAD LOAD
\\i:.\:n,.
When both HLD and HLT are true, the FD179X will then
read from or wrtta to the media. Tne "and" of HLD and HLT
appears as Status Bit 5 in Type I Status.
In summary for the Type ! commands; if h = 0 and V = 0,
HLD is reset. If h =
1 and V = 0. HLD is sei at the
beginning of the command and HLT Is not sampled nor is
there an iniernal 15 ms delay. If h = 0 and V = 1, HLD is
Set neai Ihe end of ine command. an internal 15 ms OCCurs,
and Ihe FO179X wails for HLT lo be Irue. II h = 1 and V =
1. HLD is set at the beginning of the command. Near the
end of the command, after all Ihe Steps have been Issued,
an internal 15 ms delay occurs and the FD179X Ihen waits
lor HLT to occur.
For Type II and III commands with E Nag olt, HLD is made
active and HLT Is sampled unlil true. With E flag on. HLD is
made active, an intomal 15 ms delay occurs and Ihen HLT
is sampled unlil true.
RESTORE (SEEK TRACK 0)
Upon receipl of ihis command the Track 00 fTROO) input is
sampled. II TR00 is active lo« indicating Ihe Read-Write
head ispositionedover track 0, ihe Track Register is loaded
with zeroes and an inlenupi is generated. If TR0O is not
aclive Iow, siepping pulses (pins 15 loi6)at a rate specihed
by theM r0 lield are issued until the TRCOinpul isaclivated.
AI this time the Track Register is loaded with zeroes and an
Interrupt is generaled. II the TR0O input does not go aclive
Iow afler 255 stepping puises. Ihe FD179X terminates
Operation, interuipts, and sals the Seek error Status bit.
providing Ihe V flag is sot. A verification Operation also
takes place il the V flag Is set. The h bit allawa the head to
be loaded at Ihe Start of command. Note that Ihe Restore
command is executed when MR gces Irom an active toan
inactive stale and that the DRO pm stays Iow.
SEEK
This command assumes that the Track Register contains
Ihe track number ol the current position ol the ReadWrite
head and the Dala flegisier contains Ihe desired track
number. The FD179X will updale the Track register and
issue stepping pulsos in the appropriale direction until the
contents of Ihe Track rogislerare equal lo the Contents oi

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