Sharp RX-P1H Technisches Handbuch Seite 40

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7. SIGNAL PROCESSING LSI
(SYS IC102 : LR3822A)
7-1. Outline
This LSI is designated to process the digital signals of R-DAT
and is combined with COR IC 101 (LR3823B).
Its main functions are encoding and decoding of digital signal
written on tape. In record mode it executes fetching of input signal
from A/D converter of digital interface into memory, interleave,
addition of subcode, 8-10 modulation, addition of sync signal and
ATF signal and generation of record signal.
In playback mode it executes fetching of playback data into
memory, deinterleave, fetching of data from memory into D/A
converter, and output of subcodes to microcomputer.
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7. SIGNALVERARBEITUNGS-LSI
(SYS 1C102: LR3822A)
7-1. Uberblick
Dieser LSI dient zur Verarbeitung der digitalen Signale von
R-DAT und ist mit COR 1C101 (LR3823B) kombiniert.
Seine Hauptfunktionen sind die Codierung und Decodierung der
auf Band aufgezeichneten digitalen Signale. Im
Aufnahme-Modus fuhrt er den Abruf des Eingangssignals vom
A/D-Wandler des Digital-interface in den Speicher,
Verschachtelung, Hinzuftigung von Subcode, 8-10 Modulation,
Hinzufigung von Synchronsignal und ATF-Signal und
Erzeugung des Aufnahmesignals durch.
Im Wiedergabe-Modus fuhrt er den Abruf der Wiedergabedaten
in den Speicher, Entschachtelung, Abruf von Daten aus dem
Speicher in den D/A-Wandler und Ausgabe von Subcodes an
den Mikrocomputer durch.
76, 77PIN
FROM COMMAND
MICRO CLOCK MICRO
COMPUTER COMPUTER
DATA INTERFACE
78~8 4,
86PIN
SYSTEM SETTING
SUBCODE ee
PROCESSING |__|
LP, 4CH CONVERSION
CIRCUIT
16 12,12 ~16BIT
CONVERSION
INTERPOLATION
CIRCUIT
RX-P1H RX-P1H
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7. LSI DE TRAITEMENT DES SIGNAUX
(SYS IC102: LR3822A)
7-1. Généralités
Ce circuit d'intégration a grande échelle a pour réle de traiter les
signaux numériques de R-DAT et est combiné avec le circuit
COR IC 101 (LR38238).
Ses fonctions principales sont le codage et le décodage des
signaux numériques écrits sur la bande. En mode
d'enregistrement, il prend le signal d'entrée du convertisseur A/N
de l'interface numérique pour le mettre dans la mémoire, et
effectue l'imbrication, l'addition de sous-codes, la modulation
8-10, l''addition du signal de synchronisation et du signal ATF, et
la génération du signal d'enregistrement.
En mode de lecture, il prend les données de lecture et les met
danslamémoire, et effectue la désimbrication, prendles données
de la mémoire pour les mettre dans le convertisseur N/A, et sort
les sous-codes vers le microprocesseur.
TRANSFER
CLOCK
Gs)
18. 816MHz
6. 272MHz
ol
OUTPUT
Gs)
_DRUM SYNC
8) SIGNAL
TSCK
SYSTEM CONTROLLER
RECORD
SIGNAL
9 RCSG
MODULATION CIRCUIT
6) PLAYBACK
DATA CLOCK
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ADDRESS CONTROL
O O DATA ADRESS
Cf BUS BUS
ee
AD/DA CONVERTER
DATA
TO
MAIN MEMORY
Figure 7-1 Internal block diagram of signal processing system control
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7-2. Explanation of internal Functions
1. System Controller
The frequency of crystal oscillator XL101(18.816 MHz) externally
provided is divided to generate the slot clock signal for correction
of internal memory access, and at the same time the clock
frequency from the transfor clock input on pin 66(FCH terminal).
is divided to generate the clock signals of symbol, block and frame
which compose the basic format of DAT recording signal. The IC
internal control signal is outputted, and pin 75 (DRMSYNC) is
outputted as sync signal of frame to the external terminal, and
68-pin (TSCK) is outputted as sync signal of servo drum rotation.
Since the transfer clock differs depending on the drum diameter,
it is necessary to input into the 66-pin (FCH) terminal the clock
suited to the applied drum diameter. When the drum diameter is
300, 20 and 159, this IC outputs terminal transfer clock 9.408
MHz, 6.272 MHz, and 4.764 MHz to their terminals 57-pin
(DSVCK), 55-pin (D20CK) and 7-pin (ECCCK), respectively.
Therefore, if these signals are inputted into the 56-pin (FCH)
terminal, any externally provided oscillation circuit is not
necessary.
2. Modulation Circuit
This circuit is designated to generate the record signals. Data to
be recorded is read from the externally provided main memory
1C103 (256 K RAM) through the data bus. The read data is subject
to 8 - 10 conversion together with the ID code which has been
set by the microcomputer interface, sync signal and ATF signals
are added, and the obtained signal is outputted to pin 70 (RCSG).
Moreover, the record current control signa! of ATF signal area is
outputted to pin 72 (ATFMAD), and the head record/playback
switching signal is outputted to pin 71 (HEACH).
3. Command Decoder
Data transfer to and from the microcomputer is executed through
the 8-bit data bus. The content of this data bus is divided into
commands and data. In this command decoder the command
is classified, and the signal to control data fetch from
microcomputer bus or output to the internal block is generated.
4. Address Control
The 256 bit main memory is addressed. The control signals,
WRITE ENABLE, CHIP ENABLE, OUTPUT ENABLE, etc. and
address control signal are outputted together to the terminals Ao
to A14, 50-pin (RAMWE), 57-pin (RAMCE), and 55-pin (RAMCE).
The address counter consists of AD/DA data access counter,
parity generation and error correction counter, record/playback
data access counter, subcode data access counter, memory
clear and refresh counter. The counters are changed over so that
the signal is outputted to the address bus. So as to prevent overlap
of access the priority circuit is provided.
5. Interpolation Circuit
lf error correction cannot be executed (if the error rate is
degraded, error correction may be disabled), playback data sent
to the D/A converter is interpolated from the intermediate values
of the preceding and subsequent data, an error signal is output
to pin 87 (DFLAG terminal).
6. LP, 4ch Conversion Circuit
RX-P1H is used
In 32 kHz long play mode or 32 kHz 4ch mode this circuit is used
to compress the 16-bit data to 12-bit data or to change the 12-bit
compressed data to 16-bit data. It includes a conversion circuit
which converts the 12-bit data for 8-bit access when datais written
into or reading from the main memory.
7. Subcode Processing
The subcode ID and PACK data recording/playback is executed
through the microcomputer interface. In the record mode the
parity is generated for the ID data sent from the microcomputer,
and the data is sent to the modulation circuit. Inplayback mode
the data with correct parity is sent to the microcomputer. For the
PACK data, the parity of C1 series is generated through the main
memory (record mode) or dual error correction (in playback
mode) is executed, and then the data is sent tothe modulation
circuit or microcomputer.
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