Digital Interface - Sharp Rx-P1H Technisches Handbuch

RX-P1H
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6-2. Explanation of Internal Functions
1. Demodulation Circuit
Sync signal is detected in the playback signal, 8-10 demodulation
is executed, and after ID code parity check the playback data is
outputted serially. This signal is written in the main memory
through another LSI IC 102 [SYS]. The detected sync signal and
parity check data are outputted to the 78-pin MSYNC terminal
and 73-pin IDP terminal for monitoring.
2. Error Correction Circuit
Parity generation in record mode and error correction in playback
mode are executed. The circuit is composed of 6 syndrome
calculation circuit and Galois group operation circuit,
accumulator, register groups and instruction ROM designated to
control them. In record mode data is read from the main memory
through IC102[SYS], and syndrome calculation is executed. 4
and 6 parities for C1 and C2 are generated and written in the
main memory. In playback mode data is read from the main
memory through IC 102[SYS], and error detection and correction
are executed based on the result of syndrome calculation (dual
correction in C1 series, dual correction and quintuple loss
correction in C2 series). The result of error detection with C1 is
outputted to the C1ERR terminal for monitoring.
3. Digital Interface
By frequency division of clock of the externally provided crystal
oscillator (frequency 512 times as high as FS, FS = 48 kHz and
FS = 44.1 kHz are selected) the digital interface control signal is
generated. In the playback mode the music signal (D/A datd) is
converted to the digital interface format with this control signal
and then output.
When a digital signal is input in the record mode, the music signal
(D/A data) is demodulated from the digital interface input signal.
The digital interface channel status signal is set and read through
the microcomputer interface (adaptable to SCMS system). The
setting and read-out system afford serial input/output from the
independent terminal apart from the microcomputer interface
system. LR clock, double LR clock, data transfer clock and digital
filter 256 FS clock are also generated as clock for A/D, D/A
converters.
4. Microcomputer Interface
Data is transmitted to and from the microcomputer through the
8-bit data bus. The content of this data bus is command and
relevant data. In the microcomputer interface the command is
decoded to control the data transmission between microcomputer
and IC section. As for the microcomputer interface and the
content of data refer to item 6-3.
5. Level Meter
The absolute value of music signal (16 bits) of L and R channels
which are inputted into the 83-pin DADATA terminal is held at
peak and outputted to the microcomputer bus. When the
maximum value appears twice or more successively, the
over-flow signal is outputted. The peak-hold value is reset by the
microcomputer access, and the peak value between
microcomputer accesses is held.
In the 4ch mode A, Bch or C, Dch can be selected.
RX-P1H cannot be used for 4-channel operations.
6. Error Rate Counter
The C1 flag pulse is counted, and the count is outputted to the
microcomputer bus. Count is executed every about one second
(39 turns of drum), and 4-digit BCD code is outputted. In case of
all-error 9984 count is outputted.
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