Video Bias Control Circuit; Moire Cancellation Circuit - NEC MultiSync FE700 Serviceanleitung

12. Video Bias Control Circuit

The video signals are amplified to about 45Vp-p by U203 and then the signals are biased by BIAS
CONTROL CIRCUIT which is controled by U701 through U204.
The raster brightness is determined by black level at CRT cathode which is clamping DC level of the cathode
of D214, D234 and D254.
The clamping DC level is determined by R/G/B bias which is controled by U701 through U204b respectively.
18
U201
20
Pre-Amp
23
10
U204
11
OSD IC
12

13. Moire Cancellation Circuit

Moire cancellation circuit consists of the circuit of U3A1 and others. A horizontal synchronization signal (HD)
is inputted into pin11 of U3A1, and the pulse wave form of the frequency of the half of the signal is outputted
from pin9 of U3A1. The wave form of pin8 is the reversal wave form of pin9.
Similarly, a vertical synchronization signal (VD) is inputted into pin3 of U3A1, and the pulse wave form of the
frequency of the half of the signal is outputted from pin5 of IC3A1. The wave form of pin6 is the reversal form
of pin5.
Q3A3 is turned on and turned off by these.
The amplitude of the collector wave form of Q3A3 is controlled by DAC of H_MOIRE.
The effect level of Moire cancellation changes by this amplitude.
The collector signal of Q3A3 is add to U301 pin10 (H.phase conttrol) through C309.
R
9
U203
G
11
OUT-Amp
B
8
80V LINE
R243
R239
8V LINE
Q231
R.BIAS
R248
G.BIAS
B.BIAS
R
3
G
1
B
5
R263
D234 R259
R245
Q251
Q232
R246 R268
8 - 34
R223
D254 R214
R265
Q211
Q252 Q212
R266 R228
RK
GK
CRT
BK
D214
R225
R226