NEC MultiSync FE700 Serviceanleitung Seite 131

Positive H+V
Separated Hsync
Separated Vsync
To decide whether the HSYNC input is a composite sync signal or not, program should check the
frequency of VSYNC first (reset H+V bit to "0"). If the VSYNC frequency is lower than 15.25Hz (OVF2=1),
set H+V bit to "1" and check VSYNC frequency again. If VSYNC still has no frequency, that is power saving
condition, program should reset H+V bit. If it has a valid frequency, the HSYNC input is composite signal.
Frequency Calculation
Horizontal frequency and vertical frequencies calculation are done by using one 10-bit up counter. After
power is on, the SYNC processor calculates the vertical frequency first (H/V bit = "0"). A 31.25KHz clock
counts the time interval between two VSYNC pulses, then sets the FRDY bit and generates an INT1
interrupt (if IEN_S bit is "1"). The software can either use interrupt or polling the FRDY bit to read the correct
vertical frequency. After reading the REG#16H, the FRDY bit is cleared to "0", counter is reset and H/V bit is
set. The SYNC processor starts to count horizontal frequency. The horizontal frequency calculation is done
by counting the HSYNC pulses in 8.192 ms. Like the vertical frequency, the horizontal frequency can be read
when the FRDY bit is set or INT1 occurs. After reading the REG#16H, the FRDY, INT_S and H/V bits are
cleared. The SYNC processor starts to calculate the vertical frequency again, and so on.
The relationships between counter value and frequency are:
Hfreq = (counter value × 122.07) Hz
Vfreq = ( 31250 / counter value) Hz
The frequency range:
Hfreq range: 122.07 Hz to 124.8 kHz; Resolution: 122.07Hz
Vfreq range: 30.5 Hz to 31.25 kHz
If counter overflowed, the OVF1 bit will be set to "1". The counter keeps on counting until it overflowed
again. The OVF2 bit and FRDY bit will be set when counter overflowed twice.
This is designed for finding the vertical frequency bellows 15.25Hz. The program should check REG#17H
before reading REG#16H.
Polarity Detect/Control
The polarities of HSYNC and VSYNC are automatically detected and are shown in the H_POL and V_POL
bits. The polarities of HSO and VSO are controlled by the HOP and VOP bits. For example, set HOP bit
to "1", the HSO pin always outputs positive horizontal sync signal, whatever the HSYNC input's polarity is.
bypass
8 - 12
insert HSYNC