Blanking And Spot Killer - NEC MultiSync FE700 Serviceanleitung

8. Blanking and spot killer

Circuit Diagram
R3
V-SYNC
U402
8pin
R1
D1
C2
V-flyback
Description of the circuit:
1) The vertical blanking circuit completes by Q1, Q2 and peripheral circuit.
The vertical sync pulse applied to R3, R12 connected to Q2 base. Q2 is invert amplifier, then mixer
with Q1 base together for compensate vertical retrace time of the blanking pulse.
2) The vertical flyback pulse through D1, C2, R1, R2 make waveform forming and clamp. Then applied
to Q1 base, the vertical blanking amplifier of the Q1, through C3 coupling to G1 control circuit. D4 for
over voltage protect.
3) The Q6 is spot killer protect circuit, in normal power off stage.
V1 = V2 and ZD1, so Q6 off. The CRT G1 voltage is fixed at -10 ~ -100V
pulse 28Vpp. V
When power off the voltage V1 > V2, then Q6 turn on pulling V
4) When Mute set to lower the Q3 off G1 = -150V screen cut off no picture display, this mute circuit
makes active, at power ON/OFF and when mode change stage.
5) Q4 bias set up by MCU to control the V
Test points for maintenance:
1) Check D1, R3 and Q1 collector
2) G1 voltage control range = -10 ~ -100VDC
G1 off momentary voltage≒ ≒ ≒ ≒ -150VAC
R6
Q2
R12
Q1
R2 C
D4
= − (V × R11) / (R10 + R11), (V = V1 − V3).
G1
C3
V2
ZD1
T301
5pin
C5
+
G1
G1
bias of Q3, then control G1 voltage output.
CE
8 - 26
VCC
R7
D6
R11
R10
Q4
Q3
Q6
V3
VE
V1
C4
with vertical blanking
DC
to -150V to protect CRT.
#MUTE2
R8
BRIGHT
CONTROL
R9