NEC MultiSync FE700 Serviceanleitung Seite 130

SYNC Processor
The SYNC processor can : (1) separate the composite sync signal; (2) calculate HSYNC and VSYNC
frequencies; (3) detect polarities of HSYNC and VSYNC input; (4) control the output polarities of HSO and
VSO pin; (5) generate free-running horizontal and vertical sync signals for burn-in test; (6) generate self-test
pattern signal.
Composite Sync Signal Separation
The composite sync signal comes from HSYNC pin and is separated by the sync separator.
The operations of sync separator are:
- detect the polarity and covert composite sync signal to positive polarity.
- extract Vsync
Pulse width less than 6us will be filtered, the Vsync will be widened about 5.5~6.5us.
- count the pulses during the separated V sync is low, and save the counted value (NH).
- bypass the composite sync pulses before the counter equals to N
- start inserting Hsync pulses after the counter equals to N
- the period of inserted Hsync is decided by the last two bypassed Hsync.
- the pulse width of the inserted Hsync is 2us.
H.
until the separated Vsync is low.
H
8 - 11