NEC MultiSync FE700 Serviceanleitung Seite 136

SCL
SDA
1 0 1 0 0 0 0 0
In
SDA
Out
Write REG#19H to release
Shift register to data buffer
INTO
SCL
SDA
1 0 1 0 0 0 0
In
SDA
Out
Write REG#19H to release
Data buffer to shift reg
INTO
Pull low SCL
Data Byte
A
DDC2B=1
ADDR=0
R/W=0
START=1
STOP=0
DDC2B state write timing
Pull low SCL
1
A Data Byte
DDC2B=1
ADDR=0
R/W=1
START=1
STOP=0
DDC2B state write timing
8 - 17
Pull low SCL
Data Byte
A
DDC2B=1 DDC2B=1
ADDR=0 ADDR=0
R/W=0 R/W=0
START=0 START=0
STOP=0 STOP=0
Pull low SCL
A
Data Byte
DDC2B=1
ADDR=0
R/W=1
START=0
STOP=0
Pull low SCL
A
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=1
N
DDC2B=1
ADDR=0
R/W=1
START=0
STOP=1