Ssi Interface - TR-Electronic C 58 Serie Benutzerhandbuch

Installation / Preparation for commissioning

4.5 SSI interface

In the idle condition the signals Data+ and Clock+ are high. This corresponds the time
before item
With the first change of the clock pulse from high to low
monoflop (can be retriggered) is set with the monoflop time t
The time t
frequency results from the total of all the signal delay times and is limited additional by
the built-in filter circuits.
With each further falling clock edge the active condition of the monoflop extends by
the time t
With setting of the monoflop (1), the bit-parallel data on the parallel-serial-converter
will be stored via an internal signal in the input latch of the shift register. This ensures
that the data cannot change during the transmission of a position value.
With the first change of the clock pulse from low to high
(MSB) of the device information will be output to the serial data output. With each
following rising edge of the clock pulse, the next lower significant bit is set on the data
output.
When the clock sequence is finished, the system keeps the data lines at 0V (Low) for
the duration of the mono period, t
two successive clock sequences is determined and is 2 * t
Already with the first rising clock edge the data are read in by the evaluation
electronics. Due to different factors a delay time results to t
Thereby the measuring system shifts the data with the time t
Therefore at item
line break monitoring in connection with a "0" after the LSB data bit. Only to item
MSB data bit is read. For this reason the number of clock pulses corresponds the number
of data bits +1 (n+1).
Clock+
Data+
Figure 3: Typical SSI - transmission sequences
Clock+
Data+
internal
Figure 4: SSI transmission format
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(1) is following, see chart indicated below.
determines the lowest transfer frequency (T = t
M
, at last at item (4).
M
(2) a "Pause 1" is read. This must be rejected or can be used for the
t
p
1 2 3
1 2
MSB
Monoflop, can be retriggered
TR - ECE - BA - DGB - 0039 - 14
(4). With this, the minimum break time t
M
Monoflop time
4
T
n
LSB
t
D
(1) the internal-device-
.
M
/ 2). The upper limit
M
(2) the most significant bit
between
p
.
M
> 100 ns, without cable.
V
retarded to the output.
V
(3)
n+1
High
Low
t
M
High
Low
High
Low
Printed in the Federal Republic of Germany
07/30/2020
the