11.31 Pcie At The Phycore-Z500P(T) Baseboard; Table 40: Pcie X 1 Slot X6; Table 41: Pcie X 1 Slot X7 - Phytec phyCORE-Z500PT Hardware Bedienungsanleitung

11.31 PCIe at the phyCORE-Z500P(T) Baseboard

At the phyCORE-Z500P(T) are two PCIe x1 lanes available (if the Intel 82574 Ethernet is not
populated). The second PCIe x 1 lane is connected to a 5-Lane 5 Port PCIe Switch to enable the user
to use 2 PCIe x 1 and 1 miniPCEe card. The last PCIe x 1 lane is connected to the ARIA-GX FPGA.
Pin Signal
B1 ATX_12VDC
B2 ATX_12VDC
B3 N.C.
B4 GND
B5 SMB_CLK
B6 SMB_DATA
B7 GND
B8 VCC3V3S
B9 N.C.
B10 VCC3V3A
B11 #PCIE_WAKE
B12 N.C.
B13 GND
B14 PCIE_TXN_4
B15 PCIE_TXP_4
B16 GND
B17 #CLK_PCIESLOT0_OE
B18 GND
Table 40: PCIe x 1 slot X6
Pin Signal
B1 ATX_12VDC
B2 ATX_12VDC
B3 N.C.
B4 GND
B5 SMB_CLK
B6 SMB_DATA
B7 GND
B8 VCC3V3S
B9 N.C.
B10 VCC3V3A
B11 #PCIE_WAKE
B12 N.C.
B13 GND
B14 PCIE_TXN_5
B15 PCIE_TXP_5
B16 GND
B17 #CLK_PCIESLOT1_OE
B18 GND
Table 41: PCIe x 1 slot X7
© PHYTEC Messtechnik GmbH 2009
The phyCORE-Z500P(T) on the Carrirer Board
L-732e_0
Signal
PCIE_SLOT0_PRESENT
ATX_12VDC
ATX_12VDC
GND
N.C.
N.C.
N.C.
N.C.
VCC3V3S
VCC3V3S
#RESET
GND
CLK_PCIE_SLOT4
#CLK_PCIE_SLOT4
GND
PCIE_RXP_4
PCIE_RXN_4
GND
Signal
PCIE_SLOT5_PRESENT
ATX_12VDC
ATX_12VDC
GND
N.C.
N.C.
N.C.
N.C.
VCC3V3S
VCC3V3S
#RESET
GND
CLK_PCIE_SLOT5
#CLK_PCIE_SLOT5
GND
PCIE_RXP_5
PCIE_RXN_5
GND
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
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