11.35 Address-Map / Usb-Tree; Table 45: I/O-Address Map; Table 46: I²C-Address Map (8-Bit); Table 47: Usb Port Usage - Phytec phyCORE-Z500PT Hardware Bedienungsanleitung

phyCORE-Z500P(T)

11.35 Address-Map / USB-Tree

I/O-Addresses Name
0x800 SPISEL
0x801 SPIDSEL
0x80 Debug Port 0x80
0x81 Debug Port 0x80
0x378 LPT
0x3f8 COM1
0x2f8 COM2
Table 45: I/O-Address Map
I²C-Addresses Description
0xA0 SPD EEPROM (U8)
TBD SMB Interface of 82574L (U16)
0xD2 SMB Interface of Clock Chip ICS9UM633 (U26)
0xEE Slave Interface of PCIe switch 89HPES5T5 (U1)
0xBE Master Interface of PCIe switch 89HPES5T5 (U1)
Unknown SMB Interface of GPS chip LEA-5H
Table 46: I²C-Address Map (8-bit)
USB-Port ID
0 ---
1 ---
2 ---
3 ---
4 1bc7:1003
5 1546:01a5
6
7 0403:6011
Table 47: USB Port usage
94
Description
Read/write to the SPI-Flash with activating /CS
Read/write to the SPI-Flash with deactivating /CS
Write only Debug Port
Write only Debug Port
Printer-Port (IRQ-5)
Serial Port 1 (IRQ4)
Serial Port 2 (IRQ3)
Description
Low-/Full-/High-Speed Host at X27
Low-/Full-/High-Speed Host at X27
Low-/Full-/High-Speed Client or Host at X26
Low-/Full-/High-Speed Host Universal LVDS interface X29 / USB-Header X5
GSM/UMTS Module U11 at full speed
Full speed Interface of GPS chip LEA-5H
ONLY High-Speed Host at X5
ONLY High-Speed to Quad FTDI U42
Location
phyCORE
phyCORE
phyCORE
Baseboard
Baseboard
Baseboard
© PHYTEC Messtechnik GmbH 2009
Location
phyCORE
phyCORE
Baseboard
Baseboard
Baseboard
Super-IO
Baseboard
Super-IO
Baseboard
Super-IO
L-732e_0