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phyCORE-Z500P(T)
MMC2_DATA1
MMC2 dataline 1
MMC2_DATA2
MMC2 dataline 2
MMC2_DATA3
MMC2 dataline 3
MMC2_DATA4
MMC2 dataline 4
MMC2_DATA5
MMC2_dataline 5
MMC2_DATA6
MMC2 dataline 6
MMC2_DATA7
MMC2 dataline 7
According to the Intel® Design guide, the maximum recommended trace length from the SCH to the
MMC/SDIO connector should be less or equal 127 mm (5000 mils).
6.4
SDVO
The Intel® SCH has a digital display channel capable of driving SDVO adapters that provide
interfaces to a variety of external display technologies (e.g., DVI, TV-Out, analog CRT).
Signal-Name
Description
SDVO TVCLKIN pos.
SDVO_TVCLKIN
signal
SDVO TVCLKIN neg.
#SDVO_TVCLKIN
signal
SDVO management
SDVO_CTRLDATA
data
SDVO management
SDVO_CTRLCLK
clock
SDVOB Clock pos.
SDVOB_CLK
signal
SDVOB Clock neg.
#SDVOB_CLK
signal
SDVO_INT
SDVO INT pos. signal
#SDVO_INT
SDVO INT neg. signal
SDVOB STALL pos.
SDVOB_STALL
signal
SDVOB STALL neg.
#SDVOB_STALL
signal
SDVOB Red pos.
SDVOB_RED
signal
SDVOB Red neg.
#SDVOB_RED
signal
SDVOB green pos.
SDVOB_GREEN
signal
SDVOB green neg.
#SDVOB_GREEN
signal
SDVOB blue pos.
SDVOB_BLUE
signal
SDVOB blue neg.
#SDVOB_BLUE
signal
24
IPU 75k Ohm
90
SR 47 Ohm
IPU 75k Ohm
94
SR 47 Ohm
IPU 75k Ohm
96
SR 47 Ohm
IPU 75k Ohm
98
SR 47 Ohm
IPU 75k Ohm
100
SR 47 Ohm
IPU 75k Ohm
104
SR 47 Ohm
IPU 75k Ohm
106
SR 47 Ohm
Nr. @
On-board
Type
X2
circuit
IPU 50 Ohm
185
O LVDS
SC 100nF
IPU 50 Ohm
O LVDS
187
SC 100nF
192
PU 10k Ohm
CMOS3.3
191
PU 10k Ohm
CMOS3.3
IPU 50 Ohm
O LVDS
186
SC 100nF
IPU 50 Ohm
O LVDS
188
SC 100nF
IPU 50 Ohm
178
O LVDS
SC 100nF
IPU 50 Ohm
180
O LVDS
SC 100nF
IPU 50 Ohm
O LVDS
193
SC 100nF
IPU 50 Ohm
O LVDS
195
SC 100nF
IPU 50 Ohm
194
O LVDS
SC 100nF
IPU 50 Ohm
O LVDS
196
SC 100nF
IPU 50 Ohm
206
O LVDS
SC 100nF
IPU 50 Ohm
O LVDS
208
SC 100nF
IPU 50 Ohm
O LVDS
200
SC 100nF
IPU 50 Ohm
202
O LVDS
SC 100nF
© PHYTEC Messtechnik GmbH 2009
I/O
CMOS3.3
I/O
CMOS3.3
I/O
CMOS3.3
I/O
CMOS3.3
I/O
CMOS3.3
I/O
CMOS3.3
I/O
CMOS3.3
Trace length on
phyCORE
I/O
I/O
Remark
L-732e_0
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