Jtag; Smb; Clock-Generator (U26) - Phytec phyCORE-Z500PT Hardware Bedienungsanleitung

phyCORE-Z500P(T)
6.10

JTAG

There are three devices on the phyCORE-Z500P(T) where JTAG can be used to do a boundary scan
or reprogram the device. These devices are the Z500P(T), the SCH and the Altera EPM240/570.
Signal-Name Description
PLD_TDO TDO from PLD
PLD_TDI TDI from PLD
PLD_TCK TCK from PLD
PLD_TMS TMS from PLD
XDP_TRST TRST from CPU
XDP_TCK_0 TCK from CPU
XDP_TDI TDI from CPU
XDP_TDO TDO from CPU
XDP_TMS TMS from CPU
SCH_TDO TDO from SCH
SCH_TDI TDI from SCH
SCH_TCK TCK from SCH
SCH_TMS TMS from SCH
SCH_TRST TRST from SCH
6.11

SMB

The Intel® SCH provides an SMB interface which is used on board to connect an SPD-EEPROM
(U3), the Clock-Generator (U26) and the management port of the 82574 Ethernet controller.

6.11.1 Clock-Generator (U26)

On the phyCORE-Z500P(T) a clock-generator from IDT is used to generate the different clock
domains for i.e. PCIe Slot 0/1, PCIe core, CPU-BCLK, SCH-BCLK, Display-PLL A/B.
Both PCIe clocks can be separately enabled by driving CLK_SLOT1_OEn / CLK_SLOT2_OEn to
GND.
The Clock-Generator is connected to the SMB bus and can be accessed with I²C address 0xD2.
32
on-board
Nr. @ X2
circuit
115 O CMOS3.3
117 PU 10k Ohm I CMOS3.3
119 PD 10k Ohm I CMOS3.3
123
PU 10k Ohm I CMOS3.3
125
PD 56 Ohm I CMOS1.05
127
PD 56 Ohm I CMOS1.05
128
PU 56 Ohm I CMOS1.05
130
PU 56 Ohm O CMOS1.05
132
PD 56 Ohm I CMOS1.05
116
PU 56 Ohm OD CMOS1.05
IPU 5k Ohm
118
PU 56 Ohm
I CMOS1.05
IPU 5k Ohm
120 PU/PD 56 Ohm
I CMOS1.05
IPU 5k Ohm
124
PU 56 Ohm
I CMOS1.05
IPU 5k Ohm
126 PD 56 Ohm
I CMOS1.05
© PHYTEC Messtechnik GmbH 2009
Type Remark
L-732e_0