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phyCORE-Z500P(T)
NOTE:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin. Those pins marked
as "N/A" have a range of applicable values that constitute proper operation.
Table 1:
Pinout of the phyCORE-Connector X2
Pin
Name
1,3,5,7,9
VCC5VA
11
GND
13
HDA_SDI_0
15
HDA_SDI_1
17
#HDA_DOCKEN
19
HDA_DOCKRST
21
HDA_RST
23
FWH_BSEL
25
FWH_EN
27
#SMI
29
#PM_SLP_S3
31
#PM_SLP_S4
33
#H_INIT
35
SMB_CLK
37
SMB_DATA
39
CLK_LPC_PORT80
41
GND
43
CLK_LPC_FWH
45
LPC_FRAME
47
#LPC_CLKRUN
49
LPC_SERIRQ
51
GND
53
GPIO_SUS0
55
#PM_PWRBTTN
57
GPIO_0
59
GPIO_2
61
GND
63
GPIO_4
65
GPIO_6
67
GPIO_8
69
#H_IERR
71
GND
73
MMC_0_LED
75
#MMC0_CD
8
Description
Main Power Supply
Ground
Disable on board FWH
System Managment Interrupt
S3 control-signal
S4 control-signal
System-Managment-Bus Clock
System-Managment-Bus Data
LPC Clock used for Port 80
Ground
LPC Clock for FWH
LPC Frame Signal
LPC....
LPC interrupt line
Ground
Debounced copy of #SMC_ONOFF
Ground
Ground
Activity output MMC0
Card detect MMC0
© PHYTEC Messtechnik GmbH 2009
Type
Power
Power
Bankselect input
for BIOS backup
Input (PU)
output
output
Bidir (PU)
output
Power
output
Power
output
IO
IO
Power
IO
IO
IO
Power
output
Input (PU)
L-732e_0
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