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phyCORE-Z500P(T)
157
USB_DP_0
159
USB_DN_0
161
GND
163
#USB_OC_0
165
LA_DATAP_0
167
LA_DATAM_0
169
L_DDC_CLK
171
LA_DATAP_1
173
LA_DATAM_1
175
GND
177
LA_DATAP_3
179
LA_DATAM_3
181
SMC_SHUTDOWN
183
L_BKLTEN
185
SDVO_TVCLKIN
187
#SDVO_TVCLKIN
189
GND
191
SDVO_CTRLCLK
193
SDVOB_STALL
195
#SDVOB_STALL
197
GND
199
MDI_PLUS0
201
MDI_MINUS0
203
LAN_LED0
205
MDI_PLUS1
207
MDI_MINUS1
209
GND
211
MDI_PLUS2
213
MDI_MINUS2
215
LAN_LED1
217
MDI_PLUS3
219
MDI_MINUS3
221
GND
223
CLK_PCIE_SLOT0_CON
225
#CLK_PCIE_SLOT0_CON
227
#PCIE_WAKE
229
GND
231
PCIE_TXP_1_CON
233
#PCIE_TXN_1_CON
235
#CLK_SLOT0_OE
10
USB Port 0 pos. Dataline
USB Port 0 neg. Dataline
Ground
Over current USB port 0
LVDS data group 0 pos. signal
LVDS data group 0 neg. signal
DDC clock
LVDS data group 1 pos. signal
LVDS data group 1 neg. signal
Ground
LVDS data group 3 pos. signal
LVDS data group 3 neg. signal
...
LCD Backlight enable
SDVO TVCLKIN pos. signal
SDVO TVCLKIN neg. signal
Ground
SDVO management clock
SDVOB STALL pos. signal
SDVOB STALL neg. signal
Ground
Ethernet MDI0 pos. signal
Ethernet MDI0 neg. signal
Ethernet Activity Led
Ethernet MDI1 pos. signal
Ethernet MDI1 neg. signal
Ground
Ethernet MDI2 pos. signal
Ethernet MDI2 neg. signal
Ethernet Link Led
Ethernet MDI3 pos. signal
Ethernet MDI3 neg. signal
Ground
PCIe pos. clock for Slot 0
PCIe neg. clock for Slot 0
Wake Signal
Ground
First PCIe Transmit pos.
First PCIe Transmit neg.
Output enable for Slot 0 clock
© PHYTEC Messtechnik GmbH 2009
Diff bidir
Diff bidir
Power
input
Diff output
Diff output
Output (PU)
Diff output
Diff output
Power
Diff output
Diff output
output
output
Power
Output (PU)
Power
Diff bidir
Diff bidir
Output (OD)
Diff bidir
Diff bidir
Power
Diff bidir
Diff bidir
Output (OD)
Diff bidir
Diff bidir
Power
Diff output
Diff output
input
Power
Diff output
Diff output
Input (PU)
L-732e_0
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