Phytec phyCORE-Z500PT Hardware Bedienungsanleitung Seite 8

phyCORE-Z500P(T)
Table 29: Secure Digital / Multi-Media-Card X32 ...........................74
Table 30: FPGA JTAG pin header (X10)........................................76
Table 31: HSMA JTAG pin header (X11) .......................................77
Table 32 PLD JTAG pin header (X12)..........................................78
Table 33: PCIe Switch JTAG-Port (X4) ..........................................79
Table 34: Z500P(T) JTAG/XDP-Port (X34) ....................................80
Table 35: US15WP(T) JTAG-Port (X35) ........................................81
Table 36: phyCORE PLD JTAG pin header (X36) .........................82
Table 37: HSMC connector X33 Bank 1.........................................83
Table 38: HSMC connector X33 Bank 2.........................................84
Table 39: HSMC connector X33 Bank 3.........................................85
Table 40: PCIe x 1 slot X6 ..............................................................87
Table 41: PCIe x 1 slot X7 ..............................................................87
Table 42: miniPCIe slot X8 .............................................................89
Table 43: LEDs at the baseboard...................................................92
Table 44: Switches at the baseboard .............................................92
Table 45: I/O-Address Map.............................................................94
Table 46: I²C-Address Map (8-bit) ..................................................94
Table 47: USB Port usage ..............................................................94
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