Sch Us15Wp(T) (U2); Lpc Bus; Table 4: Lpc-Bus Signals - Phytec phyCORE-Z500PT Hardware Bedienungsanleitung

6

SCH US15WP(T) (U2)

The System Controller Hub (SCH) integrates a graphics memory controller hub and an I/O controller
hub into one package.
The SCH provide all I/O like LPC Bus, LVDS, SDVO, SDIO/MMC, PCIe, USB, PATA, HDAudio
GPIOs, JTAG and also the DDR2-Controller, which are described on the following pages.
SCH at Ordering Code /
U2 Marking
US15WP LE82US15EC
US15WPT LE82US15EE
For more information take a look at
http://www.intel.com/design/intarch/atom500/index.htm
6.1

LPC Bus

The LPC Bus implemented in the SCH is used to connect Super-I/O controllers, Firmware-Hubs and
other low speed peripheral to the phyCORE-Z500.
The LPC bus was specified from Intel® and the specification can be downloaded from
http://www.intel.com/design/chipsets/industry/lpc.htm
Signal-Name Description
CLK_LPC_PORT80 LPC Clock used for Port 80
CLK_LPC_TPM LPC Clock for TPM
CLK_LPC_FWH LPC Clock for FWH
LPC_FRAME LPC Frame Signal
#LPC_CLKRUN LPC Clock Gate
LPC_SERIRQ LPC interrupt line
LPC_AD0 LPC Bus Address 0
LPC_AD1 LPC Bus Address 1
LPC_AD2 LPC Bus Address 2
LPC_AD3 LPC Bus Address 3
Table 4: LPC-Bus signals
© PHYTEC Messtechnik GmbH 2009
Temp.
FSB / DDR2
Range
0 – 70°C 400MHz/533MHz
-40 – 85°C 400MHz/533MHz
Nr. @ X2 on board circuit
39 SR 20 Ohm
40 SR 20 Ohm
43 SR 20 Ohm
45
47 PU 10k Ohm
49 PU 10k Ohm
44 IPU 50k Ohm
46 IPU 50k Ohm
48 IPU 50k Ohm
50 IPU 50k Ohm
L-732e_0
SCH US15WP (T) (U2)
GFX
R247
frequency
200 MHZ populated
200 MHZ populated
Type Remark
O CMOS3.3
O CMOS3.3
O CMOS3.3 Used on board for FWH
O CMOS3.3
I/O CMOS3.3
I/O CMOS3.3
I/O CMOS3.3
I/O CMOS3.3
I/O CMOS3.3
I/O CMOS3.3
R248
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