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STUDER
A729
4.8.2 Hardware
interconnections
Ports I
Ports
2
Signal
description
The
port lines
P10
to
P16
are
directly connected one to
the other
and
form a 7 bit
data bus between
the processors.
Port
line P17 of each processor is used for generate NMI pulses on the
other
processor (ES_NMI
and
CONTR_NMI
lines). Theses
lines have both
a
pull-up
resistor
so
that no pulse
is
generated by
any undefined state of a
port.
The
second port of the 6303 processor has only 5 bits and 3 of them
(P20lo
P22)
are
used
to define the functional mode
of
the processor on power-up.
After
the processor is
initialised,
these
3
port lines
can be used normally so
they
have
to
be switched over
(lC
111,
Analog Switch).
As long as the
RESET
iine
is
active,
then pins 2, 5 and 12
are
connected
to the pofis. When
RESET
goes
high
again,
then pins
1,
3
and
'13
are
switched
over.
ES_NMI:
TX_REQ:
TX-ACK:
SCG
ACCESS:
this line is used by
the
ESTRIB
processor
to
generate
an
NMI
pulse on the CONTROL processor.
CONTR
NMI:
this line is used by the
CONTROL
processor
to
generate
an
NMI pulse
on
the
ESTRIB
processor.
this line is used by the processor which generated an
NMI
pulse
to
show
that it requests
a
communication.
this line
is used
to acknowledge the communication.
this
line is used by the
CONTROL
processor
to
define which
one
(ESTRIB
or CONTROL)
has
the control
of
the
SCC.
EDITION:9.
Mäp
1990
E
4/11
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