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STUDER
4729
Address
Decoding
ESTRIB's
waiting state
4.3.4 CONTROL
The SCC
is
the
interface between
the Bus Controller
and
the
ES Bus.
lt
converls
the parallel data
of
the processor to the bus asynchroneous data format.
The
WR signal must
be
delayed for
the
SCC,
this is effected by
R101
,
C103
and
lC
103 (Note: the diode D6 gives
a
better positive egde
of the
signal, only
the
negative edge must
be
delayed).
The access
to the SCC is explained more in detail in part 4.8 of this manual
(SCC
Shared Access).
The D|L-switches are
latched by lC
112.
The
EPROM is
selected
by
the address A15 inverted
line,
thus
the
EPROM
range
is
8000
to
FFFF Hex.
Note:
the
EPROM
output is only
enabled
when
the signal
EPROM_EN,
which
is
generated
by the NAND combination
of
RD
and SCC ACCESS, is active.
This
means
that
the
EPROM
output (to the data bus) is tri-Jtate when the
CONTROL
processor
has
control over the
SCC.
The SCC's select signal
is generated by the lC 109
(HC139)
which decodes
the
address range
6000
to
TFFF Hex.
The
DIL
switch's select signal
will
be
active
for addresses
4000
to
SFFF Hex.
When
the
ESTRIB
processor has given the
control of the
SCC
to the
CONTROL
processor, it goes to
the
SLEEP
mode
(SLP)
until an NMI
interrupt
is
received.
ln
this
state,
the R/W line
is
high, the address bus is FFFF Hex and
the data bus
is
three
state.
Micro-processor System
The CONTROL processor system
is
composed by the following
items:
r
HD 63A03
RP,
8-bit CMOS
micro-processor
r
an
EPROM of
64 kByte
r
an
EEPROM
of
I
kByte
r
a
RAM of
8
kByte
r
an address bus demultiplexer
r
an address
decode circuit
r
a
shared
Serial
Communications Controller
r
two 8-bit DIL-switch
r
an interrupt latch
r
a cuewheel pulse input
r
five keyboard and display
controllers
(5
modules)
and
it
can
communicate
with the
ESTRIB
processor directly through
a 7
bit
interconnecting bus
(see
page
6).
The processor works in multiplexed mode (MODE
2), (with
internal
RAM,
without
internal
ROM).
The mode
is
defined
on power up on ports
P20
to
P21.
These ports
are
then used for the dial input and the generation of the
SCC access
signal.
The
crystal frequency
is
fixed
to 4.9152
MHz.
The
RD
and WR
signaTs
are generated by
three NAND gates (lC
117)
which decode the
RflV
signal with
the
E
clock.
EDITION:9.
MäP
1990
E
4/5
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