Chipset
4.4.2.1
PCI Express Configuration
Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│
PCI Express Configuration
│
│
PCI Express Clock Gating
│
Peer Memory Write Enable
│
Compliance Test Mode
│
PCIe-USB Glitch W/A
│► PCI Express Gen3 Eq Lanes
│
│► PCI Express Root Port 1
│► PCI Express Root Port 2
│► PCI Express Root Port 3
│► PCI Express Root Port 4
│
PCIE Port 5 is assigned to LAN
│► PCI Express Root Port 5
│► PCI Express Root Port 6
│► PCI Express Root Port 7
│► PCI Express Root Port 8
│► PCI Express Root Port 9
│► PCI Express Root Port 10
│► PCI Express Root Port 11
│► PCI Express Root Port 12
│► PCI Express Root Port 13
│► PCI Express Root Port 14
│► PCI Express Root Port 15
│► PCI Express Root Port 16
│► PCI Express Root Port 17
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.18.1259. Copyright (C) 2016 American Megatrends, Inc.
PCI Express Clock Gating
Optionen:
Disabled / Enabled
Peer Memory Write Enable
Optionen:
Disabled / Enabled
Compliance Test Mode
Optionen:
Disabled / Enabled
PCIe-USB Glitch W/A
Optionen:
Disabled / Enabled
PCI Express Gen3 Eq Lanes
Untermenü: siehe "PCI Express Gen3 Eq Lanes" (Seite 104)
PCI Express Root Port X
Untermenü: siehe "PCI Express Root Port" (Seite 105)
Beckhoff New Automation Technology CB1064-xxxx
[Enabled]
[Disabled]
[Disabled]
[Disabled]
Kapitel: BIOS-Einstellungen
│PCI Express Root Port 1
│Settings.
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│────────────────────────────────│
│→←: Select Screen
│↑↓: Select Item
│Enter: Select
│+/-: Change Opt.
│F1: General Help
│F2: Previous Values
│F3: Optimized Defaults
│F4: Save & Exit
│ESC: Exit
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Seite 103