Pci Express Configuration - Beckhoff CB3064 Serie Handbuch

Kapitel: BIOS-Einstellungen
6.4.2.1

PCI Express Configuration

Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration
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│ PCI Express Clock Gating
│ Legacy IO Low Latency
│ Peer Memory Write Enable
│ Compliance Test Mode
│ PCIe-USB Glitch W/A
│► PCI Express Gen3 Eq Lanes
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│ PCIE Port 5 is assigned to LAN
│ PCIE Port 6 is assigned to LAN2
│► PCI Express Root Port 9
│► PCI Express Root Port 10
│► PCI Express Root Port 11
│► PCI Express Root Port 12
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└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
 PCI Express Clock Gating
Optionen: Disabled / Enabled
 Peer Memory Write Enable
Optionen: Disabled / Enabled
 Compliance Test Mode
Optionen: Disabled / Enabled
 PCIe-USB Glitch W/A
Optionen: Disabled / Enabled
 PCI Express Gen3 Eq Lanes
Untermenü: siehe "PCI Express Gen3 Eq Lanes" (Seite 89)
 PCI Express Root Port X
Untermenü: siehe "PCI Express Root Port" (Seite 90)
Seite 88
[Enabled]
[Disabled]
[Disabled]
[Disabled]
Beckhoff New Automation Technology CB3064-xxxx
│PCI Express Clock Gating
│Enabled/Disable for each root
│port.
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│────────────────────────────────│
│→←: Select Screen
│↑↓: Select Item
│Enter: Select
│+/-: Change Opt.
│F1: General Help
│F2: Previous Values
│F3: Optimized Defaults
│F4: Save & Exit
│ESC: Exit
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