Pci Express Configuration - Beckhoff CB3055 Handbuch

Chipset
4.4.1.1

PCI Express Configuration

Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration
│
│ PCI Express Clock Gating
│ DMI Link ASPM Control
│ DMI Link Extended Synch Control
│ PCIe-USB Glitch W/A
│ Subtractive Decode
│
│ PCI Express Root Port 1
│► PCI Express Root Port 2
│► PCI Express Root Port 3
│► PCI Express Root Port 4
│ PCIE Port 5 is assigned to LAN
│ PCIE Port 6 is assigned to LAN2
│ PCIE Port 7 is assigned to PCIe to PCI Bridge
│► PCI Express Root Port 8
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└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.
 PCI Express Clock Gating
Optionen: Disabled / Enabled
 DMI Link ASPM Control
Optionen: Disabled / Enabled
 DMI Link Extended Synch Control
Optionen: Disabled / Enabled
 PCIe-USB Glitch W/A
Optionen: Disabled / Enabled
 Subtractive Decode
Optionen: Disabled
 PCI Express Root Port X
Untermenü: siehe "PCI Express Settings" (Seite 64)
Beckhoff New Automation Technology CB3055
[Enabled]
[Enabled]
[Disabled]
[Disabled]
[Disabled]
Kapitel: BIOS-Einstellungen
│Enable or disable PCI Express
│Clock Gating for each root
│port.
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│────────────────────────────────│
│→←: Select Screen
│↑↓: Select Item
│Enter: Select
│+/-: Change Opt.
│F1: General Help
│F2: Previous Values
│F3: Optimized Defaults
│F4: Save & Exit
│ESC: Exit
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Seite 63