Renishaw SP25M Installationsanleitung Seite 37

SP25M installation and integration guide
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PICS and interrupt status register (base
address + 10)
This read only register returns the status of the AC3 card. The status bits are shown below:
Bits 7 to 4 - Not used.
Bit 3 - PICS READ
This bit is set to '1' when PICSREAD is asserted ﴾pulled low﴿ by a device connected to the PICS interface. It is reset to '0' when PICSREAD is
unasserted.
Bit 2 - PICS PDAMP
This bit is set to '1' when PICSDAMP is asserted ﴾pulled low﴿ by a device connected to the PICS interface. It is reset to '0' when PICSDAMP is
unasserted.
Bit 1 - PICS PPOFF
This bit is set to '1' when PICS PPOFF is asserted ﴾pulled low﴿ by a device connected to the PICS interface. It is reset to '0' when PICS PPOFF
is unasserted.
Bit 0 - INTERRUPT
This bit is set to '1' when the AC3 asserts an interrupt in mode 3, or when the AC3 is receiving an interrupt in modes 4 and 5. It is reset to
'0' when the selected interrupt is not asserted.
Issued 12 2021
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