Renishaw SP25M Installationsanleitung Seite 36

SP25M installation and integration guide
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Using interrupts
The AC3 can use any of the following interrupts: IRQ3, IRQ5, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12 and IRQ15. These are selected by bits '7', '6'
and '5' of the acquisition mode select register. An interrupt is only generated when acquisition mode 3 is selected.
One of two interrupt methods is selected by bit '4' of the acquisition mode select register. When previously written with a '1', shared interrupt
operation will occur. The host PC (bus master) holds the interrupt line high with a passive pull up resistor. When the AC3 requests an interrupt
it generates an active low pulse on the interrupt line selected using a driver that generates an active low or high impedance output. This pulse
lasts for approximately 500 ns. The bus master determines that the AC3 is the source of the interrupt by polling the PICS and interrupt status
register.
NOTE: Reading any of the AC3 registers resets the interrupt bit, therefore it is essential that the polling routine reads this register
only.
After power on, reset, or after a '0' is written to bit '4' of the acquisition mode select register, level interrupt operation will occur. This is
described in the IBM PC‐AT technical reference manual. In this mode, the AC3 drives the interrupt line to logic '0' when the interrupt mode has
been selected. When an interrupt is needed, the AC3 asserts it by driving the selected interrupt line to logic '1'. The interrupt line returns to
logic '0' and the interrupt bit is cleared when any register in the AC3 is read by the bus master.
All unselected interrupt lines present a high impedance to the ISA bus, except when the ΔT bus interface is selected. When this occurs, all
interrupts will be set to logic '0'.
In either mode, after an interrupt has occurred, bit '0' of the PICS and interrupt status register is set. This bit is cleared by reading any register
in the AC3.
Interrupt testing
Simulating the use of interrupts in both modes using the ACQUIRE bit of the command register described in section
address + 13) is possible. Writing 1 to this register causes the AC3 to respond as though it has received an interrupt signal when the AC3 has
been set to acquisition modes 4 and 5. It causes the acquisition of data and the generation of an interrupt when the AC3 has been set to
acquisition mode 3.
Issued 12 2021
Command register (base
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