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PAL signal
The PAL CVBS signal from module pin 6 is input to multi-
plexer pin 4. Due to the low level on control pin 9 (note
inverter tc10), the signal is output from pin 5, and onward
via an amplifier stage tc7 / tc8 to a low pass filter. After the
LPF and buffer transistor tc9, the signal is input to pin 15 of
the comb filter IC.
In the comb filter IC, the composite video is clamped to an
internal level and then converted by a high speed 8-bit A/D
converter. The conversion frequency is four times the col-
our subcarrier frequency. Due to the PAL standard, the Fsc
on pin 45 is 4.43 MHz, thus the conversion frequency is
17.7 MHz.
A logical low on pin 41 drives the video data in to the comb
filter processing block and a logical low on pin 47 defines
the filtering method in accordance with the PAL standard.
The separate luminance and chrominance signal data is
then converted into analog form by two 8-bit D/A convert-
ers. The conversion is carried out using the same clock
frequency of 17.7 MHz.
The luminance signal is output from pin 6, via the emitter
follower tc11 into multiplexer pin 12, out from pin 14, and
then on through the emitter follower tc6 to the module
output pin 10.
The chrominance signal is output from pin 8, via tc12 into
multiplexer pin 2 and output from pin 15, and then on
through tc4 to module output pin 11.
NTSC 3.58 signal
The signal routes are exactly the same as the PAL signal
routes. The only difference takes place in the comb filter-
ing system inside the comb filter IC. Pin 47 is high, thus a
different filtering method is selected. The conversion fre-
quency is now 14.3 MHz due to the Fsc of 3.58 MHz on pin
45.
NTSC 4.43 and SECAM signals
The signal route to the comb filter IC is the same as above.
However, now pin 41 is high and thus the comb filter IC is
in bypass mode. The signal is fed only via the A/D con-
verter, memory block and D/A converter. The conversion
frequencies are 17.7 MHz (NTSC) and 17.1 MHz (SECAM).
The NTSC 4.43 and SECAM signals are fed via the comb
filter IC because the internal memory block imposes a two
line delay on the signal. If these signals were already by-
passed in the multiplexer and the received standard
changed, for example, from SECAM to PAL, a momentary
loss of sync would occur.
S-VHS signal
The S-VHS signal is input to module pins 6 (Y) and 7 (C)
and onward to the multiplexer, pins 4 and 1. Pin 1 of the
module is now low, and this causes control pin 9 to go
high, and the internal switches of the multiplexer change
to bypass mode. The luminance signal is output from pin
14 and chrominance signal from pin 15.
If the transmission is a pure monochrome signal or pure
noise, meaning that there is no burst, the signal is bypassed
like an S-VHS signal. This is because there is then no col-
our subcarrier which is needed in the signal processing.
Scan Velocity Modulation module,
VM600
General
The purpose of the Scan Velocity Modulation (SVM) mod-
ule is to increase the sharpness of the picture during inten-
sity transients of the luminance signal.
The scan velocity modulation is carried out so that the lu-
minance signal (a), which contains intensity transients, is
first differentiated and then amplified (b).
In this way the signal produced is fed to an auxiliary coil,
which is situated at the neck of picture tube. The current
which flows through the SVM coil during intensity tran-
sients modulates the deflection field (c), and thus either
speeds up or slows down the scan velocity.
Chess pattern
White
Luminance
signal
Black
SVM
Scan velocity slower
signal
Scan velocity faster
Deflection
Basic principle of Scan Velocity Modulation
The luminance signal is first derived by two consecutive
differentiators consisting of cvm2/rvm2 and cvm1/rvm1/
rvm3.
The derived signal is preamplified by transistors tvm1 and
tvm2, and then fed to the limiter stage, which consists of a
differential amplifier, transistors tvm3 and tvm4.
The limited signal is then fed via a driver stage (tvm6 and
tvm7) to transistors Tvm8 and Tvm9, which form the out-
put stage, and onwards to the SVM coil.
Grid pattern
a)
b)
c)
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