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MicroPC
5.11.6. PIF-Bus-Timing (Read)
D0 – D7
A0 – A3
/CS0 – /CS3
/RD
Symbol
tsu(cs)
Chip Select
setup time
thd(cs)
Chip Select
hold time
tsu(ad)
Address
setup time
thd(ad)
Address hold
time
tsu(d)
Data setup
time
thd(d)
Data hold
time
tw1(rd)
Read pulse
width
tw2(rd)
Read pulse
width
tdly(d)
Data delay
time
tdly(rd)
Read delay
time
tclk
Clock cycle
tsu(cs)
tsu(ad)
twd(rd)
Beschreibung
–CSn low to –RD low
(Chip Select valid to Read valid)
–RD high to –CS high
(Chip Select hold after Read invalid)
A0..A3 valid to –RD low
A0..A3 valid after –RD high
(address hold after Read invalid)
D0..D7 valid to –RD high
(Data valid to Read invalid)
D0..D7 valid after –RD high
(data hold after Read invalid)
Normal Mode
Fast Mode
READY valid to data valid delay
READY valid to Read invalid delay
Clock cycle length at CLK2 = 50 MHz
- 26 -
thd(cs)
tsu(d)
thd(ad)
thd(d)
min.
120 ns
70 ns
120 ns
70 ns
0 ns
800 ns
160 ns
1 CLK
cycle
Hardware
typ.
max.
4 CLK
cycles
2 CLK
cycles
3 CLK
cycles
2 CLK
cycles
20 ns
20 CLK
cycles
4 CLK
cycles
20ns
2 CLK
cycles
40 ns
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