Herunterladen Inhalt Inhalt Diese Seite drucken
Inhaltsverzeichnis

Werbung

Verfügbare Sprachen

Verfügbare Sprachen

Schaltpläne und Platinenabbildungen / Circuit Diagrams and Layout of PCBs
IC Blockdiagramme

IC Block Diagrams

TO PIN 2 V REF
NOISE
REDUC-
TION
IC TA 8135 P
PRE OUT 1
REC IN 1
6
5
4
TA 8135 P
-
7
ALC
REC
IN-1
1
3
NON ALC
REC
MUTE
8
ALC
DET
ALC
NON
NON ALC
14
ALC
IN-2
REC
2
ALC
10
-
GND
9
PRE
11
REC IN 2
12
13
OUT 2
NOISE
REDUC-
TION
TO PIN 2 V REF
IC CXA 1100 P
LINE IN
PB IN
REC/PB
LINE OUT
16
15
14
13
12
11
-
+
A T T 1
+
S C
D E T
A T T 2
A T T 3
CXA 1100
A T T 3
A T T 2
S C
D E T
-
A T T 1
+
+
1
2
3
4
5
6
LINE IN
V CC
PB IN
ON/OFF
LINE OUT
IC SAA 6579 T
QUAL
RDDA
VREF
MUX
VDDA
VSSA
CIN
1
2
3
4
5
6
VP1
DIFFERENTIAL
REFERENZ
DECODER
VOLTAGE
ANTI
57KHZ
BIPHASE
ALIASING
BANDPASS
SYMBOL
FILTER
(8th ORDER)
DECODER
QUALITY-
COSTAS LOOP
BIT
VARIABLE AND
COMPARATOR
GENERATOR
FIXED DIVIDER
CLOCK
SAA6579T
OSZILLATOR
REGENERATION
DEVIDER
AND SYNC
16
15
14
13
12
11
RDCL
T57
OSCO
OSCI
VDDD
VSSD
TEST
IC µPC 1330 HA
Inverter
µPC 1330 HA
Comparator
*
1
2
3
4
5
6
7
8
SW R1
GND
SW P1
CONT
GND
VCC
SW P2
GND
3 - 25
IC TDA 1311
REC OUT-1
LEFT INPUT REGISTER
LEFT OUTPUT REGISTER
6
VOL
I / V
LEFT BIT SWITCHES
16
IOL
32 (5-BIT)
11-BIT
CALIBRATED
PASSIVE
CURRENT
DIVIDER
2
V REF
SOURCES
1 CALIBRATED
OFF
SPARE
MUTE
SOURCE
15
ON
1
NON ALC
BCK
1
2
CONTROL
ALC
WS
AND
TIMING
3
DATA
IC SAA 7345 GP
V DDA
V SSA
11 11
12
REC OUT-2
SAA 7345 GP
HFIN
8
DIGITAL
HFREF
9
PLL
FRONT-
ISLICE
7
END
REC. OUT
IREF
10
DEMODULATOR
TEST1
6
10
9
TEST2
5
CRIN
13
CROUT
14
1
CL11
TIMING
ADDRESSER
CLA
29
CL16
17
CL
31
MICRO-
DA
30
RPECESSOR
INTERFACE
RAB
32
PORE
28
7
8
IC M 62413 FP
REC. OUT
64
63
62
61
60
SCOUT
7
8
VCAO1
1 1
VCA1
REF1
2
REF1
MIDIN1
3
RECONSTRUK.
MIDINF1
4
FILTER
TREIN1
5
CLOCKED
-
+
-
BASIN1
6
+
-
BASNF1
7
TESTLOGIC AND
OUTPUT
BB11
8
SELEKTOR SWITCH
TONE L1
10
9
BBO1
9
TSTLD
TONE H1
BBI1
10
TONEL1
11
-
+
BUFLI1
12
BUFLO1
13
TONEH1
14
BUFHI1
-
+
15
Microcomputer
INT
BUFHO1
16
17
18
19
20
21
9
SW R2
UMS 1 / UMS 2
Schaltpläne und Platinenabbildungen / Circuit Diagrams and Layout of PCBs
IC LM 833, NJM 4556
V IN2
V CC
V OUT2
8
7
6
RIGHT INPUT REGISTER
RIGHT OUTPUT REGISTER
NJM 4558
8
RIGHT BIT SWITCHES
I / V
VOR
+
-
IOR
1
2
3
32 (5-BIT)
11-BIT
CALIBRATED
-
PASSIVE
CURRENT
V OUT1
V IN1
V IN1
DIVIDER
SOURCES
1 CALIBRATED
SPARE
SOURCE
REF.
SOURCE
5
VDD
TDA 1311A(T)
4
C2 100nF
GND
V DD1
V SS1
V DD2
V SS2
15
16
44
43
22
MOTO 1
PLL
MOTOR
CONTROL
23
MOTO 2
EFM
ERROR
CORRECTOR
33
CFLG
FLAGS
SRAM
AUDIO
PROCESSOR
RAM
EBU
2
DOBM
INTER-
FACE
Q-CHANNEL
CRC CHECK
21
SCLK
PEAK
Q-CHANNEL
REGISTER
DETECT
20
WCLK
SERIAL
DATA
19
DATA
INTER-
FACE
VERSATILE PINS
MISC
KILL
18
INTERFACE
3
4
26
25
24
27
V1
V2
V3
V4
V5
KILL
59
58
57
56
55
54
53
52
51
50
49
VCAO2
48
VCA2
47
REF2
REF2
46
MIDIN2
45
MIDINF2
VCA
DAC
CONT
44
TREIN2
+
+ -
+ -
+
43
BASIN2
-
BASNF2
42
BB12
41
TONE L2
40
BBO2
LOGIC
TONE H2
39
BBI2
38
TONEL2
+ -
37
BUFLI2
36
BUFLO2
M 62413FP
TONEH2
35
+ -
BUFHI2
34
V CC
REF
V DD
M62413FP
33
BUFHO2
22
23
24
25
26
27
28
29
30
31
32
GRUNDIG Service
3 - 26
IC X 24 COOP
-
+
V IN2
5
CONTROL
COMMAND/ADRESS
S CL
LOGIC
INPUT/
S DA
OUTPUT
SHIFT REGISTER
BUFFER
4
+
V EE
MEMORY ARRAY
X 24 COO
IC M 3818x
UMS 1 / UMS 2
NC
1
8
Vcc
REGISTER
NC
2
7
NC
X 24 COO
NC
3
6
S CL
Vss
4
5
S DA
NC
= NO CONNECT
Vss = GROUND
Vcc = SUPPLY VOLTAGE
SDA = SERIAL DATA
SCL = SERIAL CLOCK
GRUNDIG Service

Quicklinks ausblenden:

Werbung

Inhaltsverzeichnis
loading

Diese Anleitung auch für:

Ums 2

Inhaltsverzeichnis