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UMS 11 ... UMS 12-S
IC-Blockschaltpläne / IC Block Diagrams
24
23
22
21
20
19
18
17
16
AM
OSC
AFC
AFC
AM
LOW
OUT
OSC
MPX
VCO
CUT
IN
IN
DEMOD
ALC
AM
AM
AM
RF.AMP
MIX
OSC
BUFF
AGC
MUTE
LA1832M
AM
AM
DET .
IF
LEVEL
DET
AM/FM
VCO
COMP
IF
BUFF
S-CURVE
AM/FM
SW
TUNING
DRIVE
FM
FM
DET
IF
AM
FM
REG
GND
Vcc
FM-DET
AM
AM
TU.LED
ST.LED
MIX
REG
GND
FM IF-IN
IF
1
2
3
4
5
6
7
8
9
LB 1641
T.S.D
O.C.P
MOTOR
MOTOR
DRIVE
DRIVE
FWD / REV / STOP
CONTROL LOGIC
1
2
3
4
5
6
7
8
9
10
48
47
46
45
44
43
42
41
40
39
38
37
36
35
49
+
+
+
+
50
51
RVref
RVref
RVref
RVref
52
+
53
+
LC 75394 NE
54
RVref
55
56
+
+
57
58
59
LVref
+
60
61
LVref
LVref
LVref
LVref
62
63
+
+
+
+
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GRUNDIG Service
Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
15
14
13
R
L
FLPET
OUT
OUT
2
Serial
DECODER
Data in
STEREO
SW
15
Output
STEREO
DRIVE
Enable
TRIG
FF
FF
FF
PILOT
DET16
PHASE
DET
AM/FM
PHASE
PILOT
3
10
11
12
Clock
1
Strobe
1
2
3
34
33
SW R1
GND
SW P1
CONT
32
+
31
30
29
XIN
1
RVref
28
20
XOUT
27
1 /
FMIN
14
26
2
25
AMIN
13
24
CE
2
23
DI
3
2
22
C
B
CL
4
21
I / F
LVref
DO
5
20
V
15
POWER
19
DD
ON
RESET
18
19
V
SS
17
15
16
UMS 11 ... UMS 12-S
Latch 1
Register Stage 1
Clock
Clock
Strobe
Clock
Clock
Strobe
Strobe
Clock
Clock
Strobe
2
Latch 2
Register Stage 2
3
Register Stage 3
Latch 3
4
Register Stage 4
Latch 4
5
Register Stage 5
Latch 5
6
Register Stage 6
Latch 6
7
Register Stage 7
Latch 7
8
Register Stage 8
Latch 8
Clock
Clock
Clock
Strobe Strobe
Clock
Clock
Clock
MC 14094 B
Strobe
Strobe
Inverter
µPC 1330 HA
Comparator
4
5
6
7
8
9
GND
VCC
SW P2
GND
SW R2
REFERENCE
PHASE DETECTER
PD
16
DIVIDER
CHARGE PUMP
AIN
17
UNLOCK
SWALLOW COUNTER
DETECT OR
1/16.1/17 4bits
18
AOUT
12bits programmable
DRIVER
UNIVERSAL
DATA SFEET REGISTER
11
IFIN
COUNTER
LATCH
LC 72131 M
12
6
7
8
9
10
I02
B01
B02
B03
B04
I01
3 - 5
GRUNDIG Service
Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
10
3-State Buffer 1
DC
DD
Ripple filter,
impulse noise
prevention circuit
Q1
4
IN1
9
+
CH 1
NF1
8
-
75
Q2
5
3-State Buffer 2
Q3
3-State Buffer 3
6
Bias
circuit
Q4
GND
3-State Buffer 4
7
11
Q5
3-State Buffer 5
14
Q6
IN2
+
13
3-State Buffer 6
13
CH2
Q7
NF2
3-State Buffer 7
12
14
-
75
Q8
Standby switch
11
3-State Buffer 8
ST
Q´
12
10
Clock
Clock
S
9
OSCI
ANTI
57kHz
RECONSTRUCTION
4
ALIASING
BANDPASS
FILTER
MUX
FILTER
(8th ORDER)
8
SCOUT
CONSTAS LOOP
BIPHASE
CLOCKED
7
VARIABLE AND
SYMBOL
COMPARATOR
CIN
FIXED DIVIDER
DECODER
SAA 6579
5
V
p1
V
DDA
CLOCK
REFERENCE
TEST LOGIC AND OUTPUT
3
REGENERATION
V
VOLTAGE
ref
AND SYNC
V
MODE
SSA
6
NF
Pre Out
VCC
7
6
5
300k
180k
-
Ch2
+
CH2/A
8
-
CH1/A
1
TA 8142
Ch1
+
300k
180k
2
3
12
NF
Pre Out
Gnd.
7
Vcc
BS1
6
Current limiter circuit
OUT1
5
30k
GND
4
Thermal shroff
Overvoltage
protection
protection circuit
circuit
GND
3
Current limiter circuit
OUT2
2
BS2
1
30k
LA 4550
13
14
12
V
OSCO
DDD
OSCILLATOR
QUALITY BIT
1
AND
GENERATOR
QUAL
DIVIDER
DIFFERENTIAL
2
DECODER
RDDA
16
RDCL
15
SELECTOR SWITCH
T57
TEST
V
SSD
9
10
11
CG
Out
NF
4
14
15
180k
300k
-
Ch2
+
16
Rec In
13
ALC
ALC
-
9
Rec In
Ch1
+
180k
300k
11
10
Rec Out
NF
3 - 6
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