Abgleichplan / Adjusting Plan
HM604-2
VR21 ®
+ 12V
VR23 ^ ^ VR24
X -xl® ® X-xlO
^ VR22
(fiJ X-Offset adj.
(timebase mode)
XY-Board
+ 68V (64V)
+ 140V (134V)
GND
Test socket
1 MHz
CH II
CH I
flattop, no overshoot
(R) VR2 15
VR2 1 4 (r) ® VR213
VR212
(g)
Y-GAIN
DC Trig.
VR217
VR209
(
R)
VR207®®VFi208
DC Trig.
VR216
(rWR206
W Y-GAIN
VR210
Component-Tester Y-POS. adj.
Invert
Balance
C39
VR4
1MHz
_n ©
®
Va r i a b I e
Balance
VR3
2'5mV
® VR1
DC-Balance
(r)
VR2
100Hz
(p\
5-10-20mV
n
Vy-' Attn. Balance
EY 1
VR5
®
Invert
Balance
„
VR4
C39
1MHz
JT ©
®
Variable
Balance
VR3
2-5mV
(g
VR1
DC-Balance
VR2
100Hz
5-10-20mV
^Attn. Balance
JT
1kHz
_n_
j_^
Jn
5V
C12©
0.5V C8 ©
CIO
©
©
C4 ©
I
C6
50mV
C2©
CAL-PC B
VR41
CAL.
Amplitude
D20 - 5/93 - 604-2
Anderungen vorbehalten / Subject to change without notice