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PA2/PA3
Schaltplane und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
PA2/PA3
Schaltplane und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
PA2/PA3
HV GENERATION
TIMING
& CONTROL
E'PROM
128 x 128
WORD
ADDRESS
COUNTER
COMMAND/ADRESS
REGISTER
SHIFT REGISTER
MEMORY ARRAY
SDA = SERIAL DATA
OFF
MUTE
ON
NON ALC
ALC
REC OUT-2
X24C04
(8) Voc
(4) Vss
(7) TEST
H.V. GENERATION
TIMING
& CONTROL
START CYCLE
START
STOP
i
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
(5) SDA
(6) SCL
aaa
on ee
GrRs
COUNTER
(1) Ao
wT
(PIN) DIP/SOIC
SAA 6579 T
QUAL
RDDA
VREF
VDDA
VSSA
CIN
SCOUT
MUX
>
||
fF
=
REFERENZ
VOLTAGE
BIPHASE
ANTI
S7KHZ
RECONSTRUK.
ALIASING
BANDPASS
ack
FILTER
DECODER
FILTER
8th ORDER
QUALITY-
COSTAS LOOP
es
gr
BIT
VARIABLE AND
CLOCKED
CLOCK
TESTLOGIC AND
REGENERATION
OUTPUT
AND SYNC
SELEKTOR SWITCH
SAA 7345
22|MOTO 1
MOTO 2
MOTOR
CONTROL
ERROR
CORRECTOR
FLAGS
RAM
ADDRESSER
Q-CHANNEL
CRC CHECK
|
Q-CHANNEL
PEAK
REGISTER
DETECT
VERSATILE PINS
INTERFACE
RIED
vi
lve
[v3
|va
MICRO-
RPECESSOR
INTERFACE
V5
TAA 1311 A
LEFT INPUT REGISTER
LEFT OUTPUT REGISTER
RIGHT OUTPUT REGISTER
LEFT BIT SWITCHES
RIGHT BIT SWITCHES
VOR
32 (5-BIT)
32 (5-BIT)
7
11-BIT
11-BIT
DASEIVE
CALIBRATED
CALIBRATED
| _ . ] passive
DIVIDER
CURRENT
CURRENT
DIVIDER
RIGHT INPUT REGISTER
OQURCE
OURCES
1 CALIBRATED
1 CALIBRATED
SPARE
SPARE
SOURCE
SOURCE
GRUNDIG Service
3 - 54
RDCL
157
osco
oscl
VDDD
vSsD
TEST
TSTLD
TDA 1311A(T)
VDD
NC
= NOCONNECT
Vss
= GROUND
= SUPPLY VOLTAGE
SCL = SERIAL CLOCK
GRUNDIG Service
3-55
GRUNDIG Service
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