Intel MFS5520VI Bedienungsanleitung Seite 48

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The memory slots of each DDR3 channel from the Intel
series are populated on a farthest first fashion. This holds true even for the
Independent Channel mode. Therefore, if A1 is empty, A2 cannot be populated or
used.
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The BIOS selects the Independent Channel mode by default, which enables all
installed memory on all channels simultaneously.
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Mirrored Channel mode is not available when only one processor is populated (CPU
Socket 1).
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If both processor sockets are populated and the installed DIMMs are associated with
both processor sockets, then a given RAS mode is selected only if both the processor
sockets are populated to conform to that mode.
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The minimum memory population possible is one DIMM in slot A1. In this
configuration, the compute module operates in the Independent Channel mode; RAS
is not available.
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If both processor sockets are populated, the next upgrade from the Single Channel
mode installs DIMM_D1. This configuration results in an optimal memory thermal
spread, as well as Non-Uniform Memory Architecture (NUMA) aware interleaving.
The BIOS selects the Independent Channel mode of operation.
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If only one processor socket is populated, the next upgrade from the Single Channel
mode is installing DIMM_B1 to allow channel interleaving. The compute module
operates in the Independent Channel mode.
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If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during
memory initialization and is (essentially) disabled by the BIOS. If a DDR3 DIMM has
no SPD data or is missing SPD information, the slot in which it is placed is treated as
empty by the BIOS.
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The DIMM parameter matching requirements for memory RAS is local to a socket.
For example, while Channels A/B/C can have one match of timing, technology, and
size, Channels D/E/F can have a different set of parameters and RAS still functions.
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DDR3 DIMMs on adjacent slots on the same channel do not need to be identical.
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For the Mirrored Channel mode, the memory in Channels A and B of Socket 1 must
be identical and Channel C should be empty. Similarly, the memory in Channels D
and E of Socket 2 must be identical and Channel F should be empty.
— The minimum population upgrade for the Mirrored Channel mode is DIMM_A1,
— If Mirrored Channel mode is selected and the third channel of each processor
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DIMM_B1, DIMM_D1, and DIMM_E1 with both processor sockets populated.
DIMM_A1 and DIMM_B1 as a pair must be identical, and so must DIMM_D1
and DIMM_E1, but the DIMMs on different processor sockets do not need to be
identical. Failing to comply with these rules results in a switch back to the
Independent Channel mode.
socket is not empty, the BIOS disables the memory in the third channel of each
processor socket.
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Xeon
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Intel Compute Module MFS5520VI User Guide
processor 5500