Baseband Delay Line, Icd3 - Hitachi CP2896TA Wartungshandbuch

8
Chrominance processing
From the input switch, the CVBS / C signal is fed through
the ACC amplifier to the chroma bandpass filters. PAL C,
NTSC 3.58 C (from the comb filter) and S-VHS C signals
bypass these bandpass filters in order to preserve the sig-
nal bandwidth. The chrominance is then fed to the stand-
ard identification and colour decoder stages.
The standard identification circuit is a digital circuit with
no external components. The crystals on pins 30 (refer-
ence crystal) and 31 (second crystal) specify the standards
which can be decoded. The IIC-bus is used to indicate which
crystals are connected in order to allow proper setting of
the calibration circuits. The components on pin 29 form
the colour PLL filter. Pin 23 drives the multiplexer circuit
on the comb filter module to bypass the S-VHS signals in
the multiplexer ("L") or to feed signals onwards to the comb
filter IC ("H"). In addition, pin 23 feeds out the subcarrier
frequency (Fsc) of the active crystal to the comb filter IC.
After the PAL / NTSC demodulator and SECAM
demodulator, the signals are taken to the switch stage,
which is controlled by the standard identification circuit.
Finally, the colour difference signals are output to the
baseband delay line from pins 2 (U) and 1 (V).
From the delay line, the colour difference signals are input
to pins 3 (U) and 4 (V), then onward to the switch stage
and output from pins 14 (U) and 13 (V) to the feature box
module.
Sync processing
The CVBS / Y signal is fed through the sync separator to
the horizontal PLL and to the vertical sync separator.
The main part of the sync circuit is a 432 x fH (6.75 MHz)
oscillator. This frequency is divided by 432 to lock phase
discriminator 1 to the incoming signal. The time constant
of the loop can be selected to be either fast, auto or slow
mode using the IIC-bus. The free-running frequency of the
432 x fH oscillator is determined by a digital control circuit,
which is locked to the active crystal. Components on pin
24 form the horizontal PLL. The phase loop can be unlocked
using the IIC-bus. This is to facilitate On Screen Display
information. If there is no input signal or a very noisy sig-
nal, the phase loop can be unlocked to give a stable line
frequency and hence a stable OSD.
The horizontal sync pulse (HA) is fed from the timing gen-
erator via output pin 17 to the Feature box.
The vertical divider system has a fully integrated vertical
sync separator. The divider can handle both 50 Hz and 60
Hz systems. It can either determine the field frequency
automatically or it can be set to the desired frequency us-
ing the IIC-bus.
The divider system consists of a line counter, a norm coun-
ter , a timing generator, and a controller. The system oper-
ates at 432 times the horizontal line frequency. The line
counter receives enable pulses at twice the line frequency,
so that it counts two pulses per line. This count result is
fed to the controller. The controller can be in one of three
count states, norm, near-norm or no-norm. When the coun-
ter is in the norm state, it automatically generates a verti-
cal sync pulse (VA) from the timing generator. The VA pulse
is fed via output pin 11 to the Feature box.
Noise detector
The decoder includes an internal S/N ratio detector, which
was originally designed to control the PALplus signal proc-
ess. During PALplus transmission, the detector measures
the S/N ratio of the input signal on pin 26. When the S/N
ratio is over 20dB, the signal is accepted and the helper
signal is processed in the PALplus decoder. If the S/N ratio
is below 20dB, the PALplus process is disabled, and the
signal is handled as a normal signal. The detector can be
activated / deactivated via the IIC-bus.
In the Multi Concept, this detector is used to drive the APSi
system to accept or bypass tuned channels. The detector
controls the APSi system via the IIC-bus and it works only
during the automatic channel search.
However, the limit value of the bypass criteria (fixed 20dB)
seems to be too high for this purpose and therefore the
APSi may be too sensitive and bypass channels that it could
accept.
On the other hand, if the tuning system does not include
any signal level qualification, the APSi system accepts all
multiple and very noisy channels.
Utilizing an existing detector and avoiding both above
mentioned disadvantages, an external LPF filter is imple-
mented. This filter is located at the luminance / CVBS input
(pin 26) and it consists of switching transistors tq10 / tq11,
and RC filter rq85 / cq45.
The RC-coupling is designed to filter high frequencies
(noise) from the luminance / CVBS signal.
When the S/N ratio of the tuned signal on pin 26 is over
20dB, the filter is not activated, but the channel is accepted
as such and it will be memorized and named.
If the S/N ratio is below 20dB, the detector causes a high
level on output pin 16. Transistor tq11 conducts and the
RC-coupling filters noise from the signal improving the S/
N ratio at the decoder input. When this noise-filtered sig-
nal is fed to the detector, it considers the S/N ratio to be
better than it actually is and accepts it. This channel will be
memorized, but not named.
In any case if the S/N ratio of the noise-filtered signal stays
below 10dB, it will be completely bypassed.
By tricking the detector in this way, the signal level qualifi-
cation is reduced from an S/N ratio of 20dB to 10dB.
Sandcastle
The sync part also generates a two level sandcastle pulse
(SC) from pin 10. This pulse is used only for timing pur-
poses in the baseband delay line.
IIC-bus
The decoder / sync processor is connected to the IIC-bus
via pins 5 (SCL) and 6 (SDA).The bus address is determined
by connecting pin 22 to +8 V.
The output pin 16 controls the filtering method of the comb
filter, either PAL 4.43 MHz ("L") or NTSC 3.58 MHz ("H").
The input / output pin 15 is primarily used to detect whether
the comb filter module is installed or not, by checking the
transistor tc3 (base-collector junction). In addition, pin 15
controls the comb filter IC to be in the filtering mode ("H")
or in the internal bypass mode ("L").

Baseband Delay Line, ICd3

General
The circuit TDA4665 is a delay line which requires no ad-
justments. It includes two colour difference comb filters
and uses switched capacitor techniques.
Each comb filter consists of an undelayed signal path and
a 64 µs delayed signal path.
In PAL mode, comb filters operate as a geometric adder to
carry out the requirements of PAL demodulation.
In NTSC mode, the comb filters suppress cross-colour in-
terference.
In SECAM mode, the circuit repeats the colour difference
signal on consecutive horizontal scan lines.