Reception - Hitachi CP2896TA Wartungshandbuch

4

RECEPTION

Tuner / IF
The tuner is known as a "front end" type tuner. This is
because the tuner block and IF block are both combined
into one complex module pack. Channel tuning is based
on a frequency synthesis system with a frequency range
of 48.25 MHz up to 855.25 MHz including cable and
hyperband channels.
In multistandard sets, both blocks are IIC-bus controlled.
The IIC-bus of the IF block has only one-way data traffic.
In BG standard sets, the IF block has no IIC-bus interface.
Multistandard IF block
The filter SAW501 operates as a picture signal filter. The
video IF signal is input to pins 28 and 29 of the Picture /
Sound Detector circuit, IC501.
The filters SAW502 (BG, DK, I, Nicam L) and SAW503
(Nicam L', L/L' AM) operate as sound signal filters. Stand-
ard selection takes place by diodes D501 and D502 and
transistors T502 and T503. Transistors are driven via pin 7
of the IIC-bus expander (IC502). Sound IF signals are input
to pins 31/32 (BG, DK, I, Nicam L), 1/2 (Nicam L') and 4/5
(AM L/L') of the detector circuit.
The AGC adjustment is implemented by potentiometer
P501 on pin 26. Pins 20 and 21 are inputs for standard
switches, which are controlled by the IIC-bus expander. The
AFC information is output from pin 11 to the tuner block
and onward to the IIC-bus. The AGC control is taken from
pin 27 to the tuner block. The tank coil of the FPLL-VCO is
connected between pins 14 and 19. This PLL reference coil
determines the stopping place of the found channel dur-
ing the APSi. The VCO frequency is two times video carrier
frequency, 2 x 38.9 MHz = 77.8 MHz. For L' standard re-
quirements, the VCO frequency is switched to 67.8 MHz (2
x 33.9 MHz) using standard switches on pins 20 and 21,
and adjusted by the potentiometer P502 on pin 20.
The sound IF signal is output from pin 8 and the AM signal
from pin 7 onwards to the Multistandard Sound Proces-
sor, ICa2.
The CVBS signal is output from pin 23 to the group delay
correction circuitry and amplifiers consisting of transistors
T504...514 and associated components. The CVBS signal
is then fed to the Video Matrix Switch, ICq1.
The circuit IC502 operates as an IIC-bus expander (8-bit
shift register). Transistors T515 and T516 disconnect the
IIC-bus from pins 2 and 3 in order to eliminate possible
malfunctions on the IIC-bus when the TV set is switched
off. Standard definition takes place via the IIC-bus. The
microcontroller sends data to the shift register, the out-
puts change their state according to the data and strobe
pulse latches the outputs. The strobe pulse (high level) is
taken from the microcontroller (pin 47) to the base of tran-
sistor T517 and onward to pin 1. In addition, the base re-
sistor (R556) of T517 operates as an indication of the in-
stalled IF module version. The value of this resistor de-
pends on the module version. Pin 55 of the microcontroller
senses the voltage across this resistor and the base-emit-
ter junction , and thus identifies the module version.
The data from the microcontroller determines the outputs
of IC502 according to the transmission standard as follows:
Standard pin 11 pin 13 pin 14 pin 7
B/G H L
I, K1 H L
D/K H H
L H H
Lí H H
Pin 11 drives input switches of IC501. Pin 11 is normally
high. During channel search (APSi), pin 11 goes
low. A low level on pins 27 and 28 of IC501
switches the video IF signal (instead of sound IF)
to the FPLL block. This is because the video band
is wider, and thus channel finding is more reli-
able.
Pin 13 drives the group delay correction circuitry
Pin 14 selects the output of the group delay correction
circuitry
Pin 7 selects the correct sound IF filter
Pin 6/5 drives input switches and AM demodulator, se-
lects right modulation and VCO frequency
BG standard IF block
The BG IF block is considerably simpler than the
multistandard IF block. Only one SAW filter is used and
the IIC-bus expander, group delay correction circuitry as
well as several switching transistors are omitted.
During channel search (APSi), the microcontroller (pin 47)
drives transistor T501 to conduct. A low level on pins 27
and 28 switches the video IF signal to the FPLL block in
order to make channel finding more reliable.
Tuning
Tuning is based on the APSi system (Automatic Program
search, Sorting and channel identification). The naming and
identification of the channels takes place using either the
PDC (Program Delivery Code), VPS (Video Programming
System), NI (Nation Identification) or Teletext header. Chan-
nel sorting is country dependant, and is therefore deter-
mined beforehand by the software.
pin 6 pin 5
L L H H
H H H H
L H H H
H L L L
H H H L