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Schaltungsbeschreibung / Circuit Description
Circuit Descriptions
1. Audio Path
IC400 S TV0056A
23
G1
FM in
Level
Detector 1
AGC
42,26
Level
AMPLOCK
46 , 4 1
Detector 2
Audio Demodulator Block Diagram
Note . Where two pin numbers are given two circuits exist, one for each
stereo channel. The first number is for the Right channel.
The FM audio demodulator is of the Phase Locked Loop (PLL) type.
FM signals in the tuner Baseband Video signal are filtered by C103,
R431, R424, L403, C412 which removes unwanted Video components
from FM in.
It is important that the drive level of the signals being demodulated is
fixed so that the output amplitude from the demodulator can be
predicted. To help achieve this the input signal passes through a gain
controlled amplifier G1, whose gain is set by one of two level detectors.
When a signal is first selected Level Detector 1, which senses the
combined FM signal amplitude, is used to set G1 to an approximately
correct gain. Once PLL lock has been reached Level Detector 2 is used
which accurately monitors the actual signal level within the working PLL.
When a new audio carrier is being selected the PLL must be tuned to the new
frequency. To do this S1 is closed and the Voltage Controlled Oscillator
(VCO) is adjusted by means of the Frequency Synthesiser. The VCO
frequency is read by the Frequency Counter. Once the VCO is on frequency
S1 is opened and the VCO locks onto the incoming carrier of the same
frequency. The control loop feedback signal at the input of G2 carries the FM
modulation. The gain of G2 can be controlled to handle different FM
deviations. Loop stability is maintained by the PLL filter.
Control of all functions in the Demodulator is via the I
Note . Where two pin numbers are given two circuits exist, one for each
stereo channel. The first number is for the Right channel.
Audio Processing Block Diagram
I C 400 STV 00 56A
S3
S2
N RS
S1
6dB
-
6dB
28,27
25,24
3,53
2,54
51,52
1,55
Peak
D etector
B and-Pass
Fi l ter
2 - 4
PLL
SDA
{
Filter
I
2
C Bus
SCL
47,39
30
31
To Audio
Processi ng
G2
V/I
90
VCO
0
S1
Frequen cy
Frequen cy
Counter
Synt hesizer
49,38
C-PUMP
2
C bus from IC600.
SD A
{
2
I
C B us
SCL
30
31
S4
S6
Passi v e
A udi o
D e-em phasi s
V o l
S5
6dB
-
6dB
33,34
48,40
14,12
22,21
6,10
1.1 Noise Reduction System (NRS)
The NRS consists of a peak level detector and a controlled low pass
filter. Audio for each channel to its peak detector is band limited by an
external band-pass filter - centred on Q401 & Q408.
The output of each peak detector is a voltage stored in its NRS time
constant. This is a dc level which will vary with the amplitude of the
audio channel signal and is used to control the frequency response of
its NRS filter via a variable transconductance amplifier.
S3 is used to select the NRS system.
1.2 Passive Deemphasis
S4 is used to select the type of passive deemphasis that is applied to
each audio channel. The options are
set by external networks and are J17, and 75mS. 50mS is obtained by
adding an internal resistor in parallel with the 75mS network.
For PANDA operation NRS and 75mS are used together.
2. Microcomputer Operation
All control of functions in the satellite receiver is by the microcomputer
IC600.
The microcomputer is reset at power on by C605, R601, D601, which
prevent execution of any program code until the receiver power
supplies and peripheral devices have stabilised.
System clock is generated by an on-chip oscillator whose frequency is
set to 8MHz by XT602. A proportion of this clock signal is buffered by
Q601 and used to provide clock for IC 400 via R603, C443.
Provision is made for an additional 32.768kHz clock controlled by
XT601 for those models with 1 year timers. On models without this
facility X1 is connected to 5V.
Port 0
Bits 0 and 1 are used for detection of the voltage on pin 8 of the AUX
2 and AUX 1 SCARTs respectively. These two port bits are analogue
to digital converter inputs which measure the pin 8 voltage and can
thus sense if 4:3 or 16:9 operation is being requested on those
models with this facility.
Bits 2 to 7 are used to configure the software to various options
depending on the model variant. these inputs are normally pulled up
to 5V by a 10K resistor but are strapped to 0V by a link if the option
is invoked.
Port1
Bit 0 is the IR input. This is configured as an interrupt and is active
LOW.
Bits 1 and 2 are clock and data signals used by the factory set up bus,
and also by the receiver to receiver download facility.
Bit 5 is a counter output used to provide 22KHz tone to be added to
the LNC power for control of LNCs and other RF peripherals. This
22KHz output can be ON, OFF or pulse modulated in accordance
with the DiSEqC protocol.
Bits 6 and 7 are the inputs NO_SYNC and PK_SYNC from the sync
detector circuit. In the absence of sync NO_SYNC is high and/or
PK_SYNC is low. In the presence of sync NO_SYNC is low and
PK_SYNC is high.
Port 2
Bits 0 and 1 are the SDA (data) and SCL (clock) of the main I2C bus
used to control the Tuner, IC400, the FS version of the modulator
MOD500, and the non-volatile memory (NVM) IC601. This bus is
also made available on PL602 and PL603 for future expansion of the
receiver capabilities.
Bit 2 is the data signal LSDA used in conjunction with SCL to form
an additional I2C bus to control the extra NVM IC602 used on certain
higher spec. models.
Bits 3 to 6 are the dedicated control bus outputs to the OSD controller
IC501.
Bit 7 outputs the stand-by signal STBY, active LOW, to switch off
power to the modulator MOD500 when the receiver is in stand-by.
Port 4
Bits 3 to 5 are a three wire serial bus for future expansion.
STR 631 / STR 632
GRUNDIG Service
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