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Schaltungsbeschreibung / Circuit Description
7. Video Processing
7.1 Video Gain Control
Baseband Video from the Tuner section is ac coupled into a controlled
amplifier whose gain can be set to give the desired Video amplitude.
On receivers with an internal decoder this value is preset to suit its
requirements . On other models it is available to the user as a contrast
control. The range of adjustment is 0 to 12.8dB in 0.2dB steps.
7.2 Video Inverter
On certain models the polarity of the video signal can be set by the
invert switch so that, for instance, C band reception can be achieved.
After the invert selector switch this signal forms the BASEBAND input
to the Video Matrix.
7.3 PAL Deemphasis
The baseband signal is applied to the non-inverting input of an
amplifier which has a PAL pre-emphasis network in its negative
feedback loop. The output of this amplifier is a PAL de-emphasised
signal which is attenuated by 6dB to make it level compatible, and
forms the PAL input to the Video Matrix.
After the deemphasis the PAL signal is band limited by the 5MHz Low-
Pass Filter, followed by a Group Delay Corrector to compensate for
distortions in the filter and ac coupled into the clamp to remove the
25Hz energy dispersal waveform. This signal is the NORMAL video
input to the Video Matrix.
7.4 Video Matrix
This is a cross wire matrix of switches which can select any one of the
Video sources and make it available to each of the three outputs. In
addition to the three sources described above video is also fed to the
matrix from AUX 1, AUX 2 and the Internal Decoder, each signal being
clamped to the same level to avoid switching disturbances . Note that
not all these signals are present on all models.
Not all switching selections are made possible, for instance BASEBAND
video can only be sent to AUX 1.
Output video from the matrix is sent to AUX 1, AUX2 and the Internal
Decoder. The black level on the Internal decoder video is preset to a
suitable level for it.
All Video Matrix, Invert and Video Gain are controlled via I2C Bus from
IC600.
Block Diagram OSD-Processor
2 - 6
OSC1
CS
3
Input
SCK
4
control
circuit
SIN
5
Data
Address
control
control
circuit
circuit
Display
control
circuit
Display RAM
VDD1
20
AC
6
VSS
11
Character ROM
VDD2
7
Group
Delay
Corrector
IC400 STV0056A
Baseband Vi deo
Video Gain
From Tuner
20
13
Clamp
From Internal
5
Clamp
Decoder
11
From AUX 1
Clamp
4
Clamp
From AUX 2
NO_SYNC
{
To IC600
Sync Detector
PK_SYNC
Video Processing Block Diagram
7.5 OSD and Sync
The video to AUX 2 is also used as the feed for the On Screen Display
(OSD) insertion circuit which is used to add Menus and Status
information for the Video to be displayed on the TV. The video to AUX
2 has its sync tips clamped at a predetermined level. The Sync
separator circuit uses Q404 to slice the video between sync tip and
black level and produce sync information at its collector. This signal is
inverted by Q403 to provide the negative going sync stream for the
OSD chip IC501.
In the presence of a valid sync signal C408 is charged enough to turn
on Q402 and signal the presence of valid sync to IC200 via the
NO_SYNC signal. To further qualify the presence of sync D406, C452,
R457 form a peak sync detector to provide IC200 with the additional
PK_SYNC signal.
In the absence of valid sync IC501 is instructed to generate its own
sync so that OSD can still be used.
All control of the OSD is via the dedicated 4 wire OSD bus OSD_RESET,
OSD_CE, OSD_SCK, OSD_SDA.
The output from the OSD is used to drive the TV SCART and video
input to the Modulator.
OSC2
1
2
Synchronous signal
switching circuit
Clock oscillating
circuit
H counter
for display
Display location
detection circuit
Timing
generator
Reading address
control circuit
Display control
circuit
Shift register
Blinking circuit
STR 631 / STR 632
Low Pass
Filter
PAL
Pre-emphasi s
18
15
30
-
+
-1
Video Matrix
-6dB
PAL
Invert
BASEBAND
NORMAL
INTERNAL DECODER
AUX 1
AUX 2
Black Level
Adjust
7
To Internal
Decoder
Sync Separator
On Screen
Display
To AUX 2
To TV SCART
and modulator
HOR* VERT*
18
19
Synchronous signal
seperating circuit
OSCIN
Clock oscillating
17
circuit for generating
scnchronous signal
16
OSCOUT
14.32MHz (NTSC)
17.73MHz (PAL)
Timing generator
CVIDEO
8
NTSC
LECHA
video output
9
circuit
CVIN
10
P0/BLNK1*
12
P1/CO1*
13
P2/BLNK2*
14
P3/CO2*
15
GRUNDIG Service
2
I
C Bus
31
8
9
OSD_CS
OSD_SC K
OSD_SDA
OSD_RE SE T
OSD Bus from
IC600
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