Inhaltsverzeichnis
Werbung
Verfügbare Sprachen
Verfügbare Sprachen
Descriptions
IC7303
L64005: MPEG-2 Audio/Video Decoder
Function Overview
The L64005 is a main level, main profile MPEG-2 decoder.
It performs MPEG-2 system layer decoding of the Pack and PES layer.
The decoder outputs video through an 8-bit interface clocked at the
device clock (27MHz).
Features
– Provides a highly integrated, studio quality MPEG-2 audio/video
decoder solution.
– Decodes an MPEG-2 bit stream, including the MPEG-2 PES layer.
– Decodes an MPEG-1 bit stream as defined in ISO IS 11172,
including the MPEG-1 system layer.
– Decodes dual channel MPEG audio, LAYER 1 and 2 (MUSICAM),
with additional support for low sample rate coding and data rates
from 8 to 448 kbps.
– Operates at image sizes up to CCIR 601 resolution 720 x 480 pixels
@ 30 fps for NTSC and 720 x 576 @ 25 fps for PAL.
– Supports master or slave video timing operation.
– Integrates post processing filters for image resizing.
– Implements 3:2 pulldown and various wide screen modes, including
16:9 mode.
– Supports up to 20Mbit/s serial, or 40Mbit/s parallel, input channel
data rate.
– Supports 1-bit serial or 8-bit parallel input data formats through
external microcontroller.
– Provides 8-bit Y/C output data format in interlaced or progressive
scanned mode.
– Provides a complete on-chip channel buffer and display buffer
controls.
– Includes programmable display management.
– Interfaces to an inexpensive 8 bit microcontroller for initialization,
testing and status monitoring.
– Supports downloadable quantization tables through bitstream.
– Provides programmable channel buffer and display buffer size.
– Connects directly to commodity DRAMs.
– 16Mbits of DRAM, from four 4-Mbit regular DRAMs or one 16-Mbit
SDRAM, is required for CCIR601 resolution.
– Maintains display of images during channel errors with error con-
cealment.
– Provides selectable error concealment in audio decoder.
– Requires no external microcode or external logic.
– Optimizes input/output interfaces for glueless integration into con-
sumer video system to provide a cost effective solution.
– Operates from a single 27MHz clock, with optional additional audio
sample clock input.
110
D7
7303
L64005
109
D6
108
D5
107
D4
106
D3
105
D2
104
D1
103
D0
127
A2
126
A1
125
A0
121
ASN
132
CSN
137
INTRN
133
READ
134
WAITN
102
RESETN
130
NC1
128
NC2
119
NC3
100
NC4
81
NC5
131
CLK_GEN.
NC6
120
RES1
117
RES2
116
RES3
115
RES4
MPEG2 IN
2 - 20
INTEGRATED
MPEG AVG DECODER
LSI
AUDIO
VIDEO INTERFACE
INTERFACE
Pin
Name
I/O Function
125-127
A[2:0]
I
42
ACLK
I
70
AGND
I
79
AREQ
O
41
AS
I
121
ASDATA
O
80
AVALID
I
68
AVDD
I
71, 73-78, 83-84
BA[8:0]
O
2
BCLK
O
138-139, 36-38,
43-45, 48-50, 52-61
BD[63:0]
I/O DRAM Data
118
BLANK
O
64
CAS
O
123
CREF
O
132
CS
I
103-110
D[7:0]
I/O User Data Bus
121
ERROR
I
96
HS
I/O Horizontal Sync
137
INTR
O
69
LP2
I/O Loop Filter Connection
1
LRCLK
O
66
OE
O
159
OSD
I/O OSD Active
133
READ
I
89-95
PD[7:0]
O
65
RAS
O
102
RESET
I
82
SCLKI
I
114
SERI
I
87
SYSCLK
I
111
VREQ
O
135
VVALID
I
97
VS
I/O Vertical Sync
134
WAIT
O
67
WE
O
12, 28, 39, 47, 51, 63,
85, 98, 99, 101, 113,
122, 136, 144, 153
GND
–
11, 20, 27, 40, 46, 62,
72, 86, 112, 129, 143,
152, 160
VDD
–
81, 100, 119, 128, 130,
131, 115, 116, 117, 120 NC
–
GDV 100 D
Address
Audio Clock
Analog ground
Audio Data Request
Address Strobe
Audio Serial Data Line
Audio Data Valid
Analog Power
DRAM Address
Serial DAC Bit Clock
Composite Video Blanking
DRAM Column Address Select
Chroma Reference
Chip Select
Serial Error
Interrupt
Serial DAC L/R Clock
DRAM Output Enable
Read
Pixel Data
DRAM Row Address Select
Reset
Serial Clock In
Serial Data Input
System Clock
Video Data Request
Video Data Valid
Data Wait
DRAM Write
Ground
Power Supply
Not connected
BD31
BD30
BD29
BD28
BD27
BD26
BD25
BD24
BD23
BD22
BD21
BD20
BD19
BD18
BD17
BD16
BD15
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
GRUNDIG Service
21
22
23
24
25
26
29
30
31
32
33
34
35
36
37
38
43
44
45
48
49
50
52
53
54
55
56
57
58
59
60
61
Werbung
Inhaltsverzeichnis
