Inhaltsverzeichnis
Werbung
Verfügbare Sprachen
Verfügbare Sprachen
Descriptions
IC7110
ispLSI 2032: High Density Programmable Logic device
Function Overview
This device serves as an expansion to the Chip Select outputs of Host
Processor IC7111. Dependent from the address inputs A[18:21] and
chip select inputs CS[0:2], it outputs the chip selects for the Digital
Stream Manager, Digital Video Processor, the MPEG decoder, the I
bus controller and also the chip enable inputs for the FLASH and
EPROM memories.
It alters the system clock of 27MHz into the I
(division by 4).
It also performs the interface (glue) between the CPU and DRAM
controller.
113
A0
37
A1
38
A2
7111
39
A3
MC68340-PV25
42
A4
43
A5
44
A6
45
A7
46
A8
47
A9
48
A10
BUS INTERFACE
51
A11
52
A12
53
A13
55
A14
56
A15
57
A16
60
A17
61
A18
62
A19
63
A20
64
A21
65
A22
66
A23
33
RXD1
32
TXD1
28
CTS1N
29
RTS1N
TWO-
26
TXRDYN
27
RXRDYN
CHANNEL
SERIAL
25
RXD2
I/O
24
TXD2
OUTPUT
22
CTS2N
PORT
23
RTS2N
77
TMS
78
TCK
76
TEST
TDI
75
TDO
94
VCC11
96
GND11
119
VCC13
118
GND13
140
VCC15
Pin name
Function
A[23:0]
Address bus
ASN
Address Strobe
BERRN
Bus Error
BGACKN
Bus Grant Acknowledge
BGN
Bus Grant
BKPTN
Breakpoint
BRN
Bus Request
CLKOUT
System Clock Out
CS[3:0]N
Chip Select
CTS1N, CTS2N
Clear To Send
D[15:0]
Data bus
DACK1N, DACK2N
DMA Acknowledge
DONE1N, DONE2N
DMA Done
DREQ1N, DREQ2N
DMA Request
DSACK[1:0]N
Data and Size Acknowledge
DSN
Data Strobe
EXTAL, XTAL
Crystal Oscillator
FREEZE
Freeze
HALTN
Halt
2 - 16
2
2
C-bus clock of 6.75MHz
EXTERNAL
SYSTEM
INTEGRATION
MODULE
TWO
CHANNEL
DMA
CONTROL
Description
Lower 24 bits of address bus
Indicates that a valid address is on the address bus
Indicates an erroneous bus operation is being attempted
Indicates that an external device has assumed bus mastership
Indicates that the current bus cycle is complete
Signals a hardware breakpoint to the CPU32
Indicates that an external device requires bus mastership
Internal system clock
Enables peripherals at programmed addresses
Serial module clear to send inputs
16-bit data bus to transfer byte or word data
Output that signals an access during DMA
Bi-directional signal that indicates last transfer
Input that starts DMA process
Provides asynchronous data transfers and dynamic bus sizing
During a read cycle, DS indicates that an external device should place valid data on the data bus
Connections for an external crystal
Indicates that the CPU32 has acknowledged a breakpoint
Suspends external bus activity
IC7111
MC68340PV: Host processor
Function Overview
IC7111 is the HOST microcontroller for the DVD set with the following
features:
– CPU32-MC68020 is a derived 32-bit Central Processor Unit
– 32 address lines, 16 data lines
C-
– 2 DMA Controller for high-speed memory transfer
– 2 serial synchronous/asynchronous I/O interfaces (USART) for
communication with the Basic Engine (S2B)
– 2 independent counter/timers
– integrated drivers for TTL and ASIC, e.g. ELPD
– Clock frequency: 32.768MHz
– Clock frequency of USART interface: 3.6864MHz
BUS
ARBITRATION
CPU 32
CLOCK
CORE
ASN
DSN
R/WN
SIZ1
SIZ0
DSACK1N
DSACK0N
TIMER
TGATE2
TIN2
MODULLE
TOUT2
TGATE1
TIMER
TIN1
MODULLE
TOUT1
FC0
FC1
FC2
FC3
CS0N
CS1N
CHIP
CS2N
SELECT
CS3N
IRQ3N
PORT
IRQ5N
IRQ6N
B
IRQ7N
IACK7N
IACK6N
IACK5N
IACK4N
PORT
IACK3N
A
IACK2N
IACK1N
A24
VCC12
GND12
VCC14
GND14
GRUNDIG Service
GDV 100 D
103
104
107
106
105
111
112
36
34
35
79
81
80
69
70
71
72
1
2
3
5
4
8
9
10
114
115
116
117
120
121
122
123
110
109
130
129
Werbung
Inhaltsverzeichnis
