Beckhoff CB6293 Übersetzung Des Original-Handbuchs Seite 67

BIOS-Eintrag
PCI Express Root Port 3
Connection Type
PCI Express Clock Gating
PCI Express Power Gating
ASPM
L1 Substates
Gen3 Eq Phase3 Method
Gen4 Eq Phase3 Method
ACS
PTM
DPC
FOM Scoreboard Control Policy
Multi-VC
EDPC
URR
FER
NFER
CER
CTO
SEFE
SENFE
SECE
PME SCI
Advanced Error Reporting
PCIe Speed
Enable ClockReq Messaging
Transmitter Half Swing
Detect Timeout
P2P Support
CPU PCIE Func0 Link Disable
SA PCIe LTR Configuration
LTR
Snoop Latency Override
Non Snoop Latency Override
Force LTR Override
LTR Lock
CPU PCIe Gen3 HWEQ Config
UPTP
DPTP
CPU PCIe Gen4 HWEQ Config
UPTP
DPTP
CB6293
Optionen
Enabled / Disabled
Slot / Built-in
Enabled / Disabled
Enabled / Disabled
Disabled / Enabled
L1.1 & L1.2 / L1.1 / Disabled
Hardware / Static Coeff.
Hardware / Static Coeff.
Enabled / Disabled
Enabled / Disabled
Enabled / Disabled
Auto / Gen3 / Gen4 / Gen3 / Gen4
Disabled / Enabled
Enabled / Disabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Enabled / Disabled
Disabled / Enabled
Auto / Gen1 / Gen2 / Gen3 / Gen4
Enabled / Disabled
Disabled / Enabled
Keine
Disabled / Enabled
Disabled / Enabled
Enabled / Disabled
Auto / Manual / Disabled
Auto / Manual / Disabled
Disabled / Enabled
Disabled / Enabled
Keine
Keine
Keine
Keine
Version: 1.0
BIOS | Chipset
67