Dual C 828 Serviceanleitung Seite 5

Das Kippglied IC 404 (C 434, R 431, D 417, R 430) ist durch das Sper-
ren von Q 403 in seine Ausgangslage gebracht und der Ausgang von
IC 404, Pin 4 ist auf HIGH Pegel, damit wird der Oszillator stummge-
schaltet. Nach dem Betätigen der Playtaste Rechtslauf oder Linkslauf
(Reverse) wird das vom Prozessor ausgegebene LOW Signal über die Ent-
koppeldioden D 420 (F F1 oder D 421 (Rewind) auf das Kippglied 1C404,
Pin 1 geschaltet. Damit kippt der Ausgang IC 404 Pin 4 verzögert auf
LOW Pegel, der HF-Oszillator wird freigegeben. Mit dieser Schaltungs-
maßnahme wird ein versehentliches Anlöschen verhindert.
Reverse
Nach dem Betätigen der Playtaste Linkslauf = Reverse, gibt IC 401 an
Pin 20 ein LOW Signal an das Verzögerungsglied IC 404 Pin 8/9.
Nach ca. 200 ms wird durch ein LOW Signal am Ausgang von IC 404
Description of functions C 828
Analog section
Playback
The voltage from the soundhead (approximately 300 /IV during play-
back of the DIN reference level) is first of all amplified by transistors
O 101 and Q 102 and correspondingly equalized with the negative feed-
back network R 166, R 169 and C 141. The playback frequency res-
ponse in the treble frequency range can be corrected by modifying the
soundhead resonance with capacitors C 131,C 132, and C 135 (connec-
tion or disconnection). From 315 Hz to 4 kHz, the playback frequency
response is linearized with VR 102 (set at the factory). Switchover of
the playback equalization from 120 bis to 70 bis is caused by transistor
Q 103 becoming forward-biased. The playback level is set separately
for each head system with the VR 105 and VR 106 at the cinch output
socket to 550 mV during playback of the Dolby reference level (200
nWb/m). This setting is necessary for perfect functioning of the Dolby
circuit.
Via the A-W switch S 1 —3, the playback signal is routed to the Dolby
circuit IC 102, pin 5. If the Dolby selector switch S 8 — 1 is switched-
off, the signal is amplified linearly by approximately 26 dB within the
Dolby circuit, whilst amplification is frequency and level-depended
when the Dolby switch is activated. The output signal is routed from
pin 7 (IC 102) via the A-W switch S 1 — 7 to the headphone output
stage IC 103 pins 3 and 4, to the cinch output and, via the A-W switch
S 1 — 5, to the DIN socket.
In order to prevent switching noises from reaching the output sockets,
the output signal is shorted with transistor 0 107 and the input of the
recording amplifier is connected to 0 V with 0 110. The high signal for
muting is generated on the drive control board in the case of the follo-
wing functions: fast forward, rewind and stop.
Recording
Three different sources are provided for recording. The line input is
deactivated when the DIN input is used. The signal coming from the
line or DIN input is deactivated by connecting a mono or stereo micro-
phone. The signal at the Mic input is amplified with the noise free IC
101, whilst the signal at the DIN input is amplified with 0 601. The
signal from the line input is routed directly to the modulation divider
VR 101. From here, it is routed via the A-W switch S 1 —3 to the input
pin 5 of the Dolby circuit IC 102. The MPX filter is connected with
S 7 — 1 in order to suppress any residual pilot tone when recording
radio broadcasts.
Within the Dolby processor, the signal is branched to two different
outputs, pin 3 and pin 7 of IC 102. The signal, uninfluenced by the
Dolby process from pin 3, is routed during recording to the monitor
output (line), the display and headphone amplifier via the A-W switch
S 1 —7. The signal from pin 7 reaches the recording amplifier (0112
and 0 113) via the A-W switch S 1 —9. The recording current is set
separately for each head system with VR 107 and VR 108. lt is connec-
ted with 0 108 and 0 109, which depend on the setting of the reverse
switch S 2 — 8, and the level and equalization are matched to varying
tape types via transistors Q 111, 0 114 to 0 119. Via the trap circuit
L 103, the recording signal is routed to the soundhead and the bias is
mixed to it with VR 109 and VR 110. By connecting the resistors
R 301 to R 310 by means of the tape type selector S 3 Fe, S 4 Cr, S 5
FeCr and S 6 Met, the RF oscillator is influenced in such a way that an
optimum operating point is obtained for the various tape types. The
oscillator is muted with a HIGH signal at the base of 0305. The erase
current is set with VR 111. During playback mode, the DIN input is
isolated from the monitor signal with A-W switch S 1 — 5.
Recording level display
The output signal is routed to the headphone amplifier IC 103 both
during recording and playback. The signal for the display amplifier
(0 104) is decoupled from the output of IC 103 (pin 6) with C 151.
Pin 11 Transistor Q 413 gesperrt. Mit dem HIGH Signal am Kollektor
von 0 413 (Stecker A, Pin 6) werden die Treiberstufen für die Relais
RY 301 und RY 302 durchgeschaltet. Die Arbeitskontakte der Relais
bilden den Reverseschalter S 2.
Stummschaltung
Das Signal zur Stummschaltung wird mit Transistor Q 404 geschaltet.
Ist Q 404 durchgeschaltet, sperrt Q 429 und legt ein HIGH-Pegel an
den Steuerausgang Stecker A Pin 4. Die Stummschaltung ist eingeschal-
tet (siehe Beschreibung Analogteil). Ein LOW Signal von IC 401 Pin 18
an die Basis sperrt 0 404, damit steuert 0 429 zeitverzögert (C 431)
durch, es steht ein LOW Signal am Kollektor von 0429 an. Die Stumm-
schaltung wird aufgehoben. Mit den Funktionen FF, REWIND, STOP
und DLL EIN wird die Stummschaltung aktiviert.
The 0 dB mark is set with VR 103 and the -20 dB mark is set with
VR 104. IC 701 directly drives the LEDs and the display operates as an
inertialess band of light with dampened return (C 155 and R 185).
Reverse switch S 2
The reverse switch S 2 consists of the normally closed contacts of relays
RY 301 and RY 302. By means of a HIGH signal (plug A, pin 6) at its
base, Q 309 becomes forward-biased, 0 308 becomes briefly forward-
biased and this guarantees reliable response of the relays. Q 309 then
holds the relays after 0 308 has become negative-biased.
Device control
All device and drive functions are controlled by a 4-bit microprocessor.
The clock pulse frequency is approximately 450 kHz with CF 501 at
pins 24 and 25 of the processor IC 401.
Reset
When the C 828 is switched-on, the supply voltages reach their nominal
value, as the result of which Q 406 becomes negative-biased and applies
a HIGH level to the reset input pin 23 of IC 401. With the LOW-HIGH
edge of the pulse the program counter of the processor is set to its
start address and the processor is enabled for its functional sequences.
Inputs
The drive control buttons and the device switches pass on their Infor-
mation as active HIGH signals to the processor. The contacts RECORD
BLOCK S 508 (reverse) and S 509 (forward) correspond to a HIGH sig-
nal when a music cassette is inserted = contacts open. In this case, the
processor ignores Operation of the RECORD button.
DLL
A contactless infrared waveguide system is used. The infrared emitter
LED 506 is driven with the freely oscillating oscillator IC 402 and the
transistor Q 401 with a period of T = 1 ms, f = 1 kHz. This clocking
method ensures perfect Operation in the face of constant light and in-
terfering reflections. By means of the photo-transistor 0 501, the light
pulses are converted into electrical pulses and processed by the compa-
rator IC 402. If the beam of light is interrupted (DLL ON), a wave sha-
ped HIGH level is applied to the output of IC 402 pin 7 for the dura-
tion of the interruption, and is switched by C 406, R 417 and D 401 to
LOW level. This LOW signal is also applied when the cassette sensor
S 512 is closed (cassette removed) and Q 501 is negative-biased. When
the LOW signal is applied to pin 37 (IC 401), the processor recognizes
DLL on = cassette removed. The stop function is executed, the LED
STOP flashes, during playback mode the RECORD function is cancel-
led and the motors are switched-off. In play mode, the direction of mo-
tion is stored , the corresponding LED continues to light up and ,after inser-
tion of a cassette, the previously selected mode PLAY becomes effective.
The oscillator signal from IC 402 is decoupled at pin 1 by C 410 and,
via transistor 0 405, reaches the interrupt input of the processor (refer
to limit switch-off).
Limit switch-off
The information — tape running — is past on by a multiple magnetic
disc fixed to the drive wheel of the counter to IC 501. This IC contains
a hell element which reacts to alternating magnetic fields. The pulses
generated by IC 501 reach pin 31 of IC 401. This tape running fre-
quency is compared with the 1 kHz frequency of the DLL oscillator. If
the tape running pulses fail, for example in the case of a jerky cassette,
STOP is triggered off. If the MODE switch is in continuous play mode,
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