Hitachi CL32W35TAN Serviceanleitung Seite 59

Test Point Net Name
TP654 ISO
TP659 /PHY_RESET
TP661 CTL_0
TP662 CTL_1
TP647 PHY_POWER
TP643
TP644
TP649 OSC2
TP650 OSC1
TP653 PHY_POWER
TP633
TP634
TP635 TPA1+
TP636 TPA2-
TP637 TPB1+
TP638 TPB1-
TP652 MPC11 1394
TP651 MPC11 1394
TP641 TPA2+
TP640 TPA2-
TP639 TPA2+
VTP642 TPA2-
TP624 CNA
TP655 PC0
TP656 PC1
TP657 PC2
TP645 CPS
TP666 CPS
Sheet7 External DRAM Controller
TP735 SIZ0
TP733 CPU_D13
TP734 /CS_DRAMC
TP706 CLK_27_1
TP700 EBM_D0
TP701 EBM_D1
TP702 EBM_D2
TP703 EBM_D3
TP704 EBM_D4
TP705 EBM_D5
TP707 EBM_D6
TP708 EBM_D7
TP709 EBM_D8
TP710 EBM_D9
TP711 EBM_D10
TP712 EBM_D11
TP713 EBM_D12
TP714 EBM_D13
TP715 EBM_D14
TP716 TDO_I_DRAMC_LLC
TP717 EBMA0
TP718 EBMA1
TP719 EBMA2
TP720 EBMA3
TP721 EBMA4
TP722 EBMA5
TP723 EBMA6
TP724 EBMA7
TP725 EBMA8
TP726 EBMA9
TP716 TDO_I_DRAMC_LLC
TP727 EBM_D15
TP728 EBOE
Function
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394 Physical link power supply
IEEE1394
IEEE1394
24.576MHz CLOCK
24.576MHz CLOCK
IEEE1394 Physical link power supply
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
IEEE1394
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IEEE1394
IEEE1394
DRAM controlller data size 0
Cpu data 13
Chip select DRAM controller (External DRAM)
27 MHz clock
Data bus DRAM controller to DRAM bit 0 (External DRAM)
Data bus DRAM controller to DRAM bit 1 (External DRAM)
Data bus DRAM controller to DRAM bit 2 (External DRAM)
Data bus DRAM controller to DRAM bit 3 (External DRAM)
Data bus DRAM controller to DRAM bit 4 (External DRAM)
Data bus DRAM controller to DRAM bit 5 (External DRAM)
Data bus DRAM controller to DRAM bit 6 (External DRAM)
Data bus DRAM controller to DRAM bit 7 (External DRAM)
Data bus DRAM controller to DRAM bit 8 (External DRAM)
Data bus DRAM controller to DRAM bit 9 (External DRAM)
Data bus DRAM controller to DRAM bit 10 (External DRAM)
Data bus DRAM controller to DRAM bit 11 (External DRAM)
Data bus DRAM controller to DRAM bit 12 (External DRAM)
Data bus DRAM controller to DRAM bit 13 (External DRAM)
Data bus DRAM controller to DRAM bit 14 (External DRAM)
JTAG test data out
Address bus DRAM controller to DRAM bit 0 (External DRAM)
Address bus DRAM controller to DRAM bit 1 (External DRAM)
Address bus DRAM controller to DRAM bit 2 (External DRAM)
Address bus DRAM controller to DRAM bit 3 (External DRAM)
Address bus DRAM controller to DRAM bit 4 (External DRAM)
Address bus DRAM controller to DRAM bit 5 (External DRAM)
Address bus DRAM controller to DRAM bit 6 (External DRAM)
Address bus DRAM controller to DRAM bit 7 (External DRAM)
Address bus DRAM controller to DRAM bit 8 (External DRAM)
Address bus DRAM controller to DRAM bit 9 (External DRAM)
JTAG test data out
Data bus DRAM controller to DRAM bit 15 (External DRAM)
DRAM data output enable (External DRAM)
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