Advanced Chipset Features - Abit A-S78H Handbuch

2.4 Advanced Chipset Features

► DRAM Configuration
► HT Link Control
► PCIe Configuration
► IGX Configuration
Init Display First
TLB Cache Function
F5: Previous Values
DRAM Configuration
Click <Enter> key to enter its submenu.
You may manually set the DRAM timing parameters through its sub-items, or leave them at
their default settings according to the SPD (Serial Presence Detect) data stored in the DRAM.
HT Link Control
Click <Enter> key to enter its submenu. You may manually set the parameters through each
sub-item, or leave them at their default settings.
HT Link Width
HT Link Frequency
HT Link Tristate
UnitID Clumping
2x LCLK Mode
F5: Previous Values
2-8
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Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F6: Fail-Safe Defaults
Phoenix – AwardBIOS CMOS Setup Utility
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F6: Fail-Safe Defaults
manuals search engine
Press Enter
Press Enter
Press Enter
Press Enter
PCIe
Disabled
F7: Optimized Defaults
HT Link Control
Auto
Auto
Auto
Auto
Disabled
F7: Optimized Defaults
Item Help
Item Help
A-S78H