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Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
Name
VCC
LA[21:0]
VSS
RESET#
TDMDX
RSEL
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL1
TSD
SEL_PLL0
SEL_PLL2
MCLK
TBCK
SDIF_DOBM
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
DRAS[2:0]#
DB[15:0]
DCS[1:0]#
DQM
DSCK
DCLK
YUV[7:0]
PCLK2XSC
N
PCLKQSCN
VSYNCH#
HSYNCH#
HD[15:0]
HCS1FX#
HCS3FX#
HIOCS16#
HA[2:0]
VPP
HWR#/
DCI_ACK#
HRD#DCI_C
LK
HD[15:0]
HWRQ#
HRDQ#
HIRQ
HRST#
HIORDY
HWR#
AUX[7:0]
LOE#
LCS[3:0]#
LD[15:0]
LWRLL#
LWRHL#
NC
2 - 5
Number
1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92,
99, 104, 111,
121, 130, 139, 148, 157, 164, 172, 183,
193, 201
23:19,16:10,7:2,207:204
8,17,26,34,43,52,60,67,76,84,91,98,103,1
12,120,129,1
38,147,156,163,171,177,184,192,200,208
24
25
28
29
30
31
32
33
36
39
40
41
45
46
47
48
49
50
66:61, 58:53
69
70
71
74:72
96:93, 90:85, 82:77
97, 100
101
102
105
115:113, 110:106
116
117
118
119
141:140, 137:131, 128:122
152
153
151
158, 155:154
159
149
150
141:140, 137:131, 128:122
142
143
144
145
146
149
169:165, 162:160
170
176:173
197:194, 191:185, 182:178
198
199
37, 38, 42, 203:202
I/O
Definition
3.65 V ± 150 mV .
I
O
Device address output.
I
Ground.
I
Reset input, active low.
O
TDM transmit data
I
ROM Select
RSEL
Selection
0
16-bit ROM
1
8-bit ROM
I
TDM receive data.
I
TDM clock input.
I
TDM frame synch.
O
TDM output enable, active low.
O
Audio transmit frame sync.
I
Select PLL1.
O
Audio transmit serial data port.
I
Select PLL0.
SEL_PLL2 SEL_PLL0 Clock Output
0
0
0
1
1
0
1
1
Select PLL2. See the table for pin number 33.
I/O
Audio master clock for audio DAC.
I/O
Audio transmit bit clock.
O
S/PDIF (IEC958)Format Output.
I
Audio receive serial data.
I
Audio receive frame synch.
I
Audio receive bit clock.
I
Analog PLL Capacitor.
I
Crystal input.
O
Crystal output.
O
DRAM address bus.
O
Column address strobe, active low.
O
Output enable, active low.
I
Clock enable, active low.
O
DRAM write enable, active low.
O
Row address strobe, active low.
I/O
DRAM data bus.
O
SDRAM chip select [1:0], active low.
O
Data input / output mask.
O
Clock to SDRAM.
I
Clock Input(27MHz).
O
8-bit YUV output.
I/O
2X pixel clock.
I/O
Pixel clock.
I/O
Vertical synch for screen video interface,
programmable for rising or falling edge, active
low.
I/O
Horizontal synch for screen video interface,
programmable for rising or falling edge, active
low.
O
Host data bus
O
Host select 1.
O
Host select 3.
I
Device 16-bit data transfer.
I/O
Host address bus.
I
Peripheral protection voltage.
I,I
Host write/DCI Interface Acknowledge Signal,
active low.
I,I
Host read/DCI Interface Clock.
I/O
Host data bus.
O
Host write request.
O
Host read request.
I/O
Host interrupt.
O
Host reset.
I
Host I/O ready
O
Host write request.
I/O
Auxiliary ports.
O
Device output enable, active low.
O
Chip select[3:0], active low.
I/O
Device data bus.
O
Device write enable, active low.
O
Device write enable, active low.
No Connect pins. Leave open
GDV 130...
2.5 x DCLK
3 x DCLK
3.5 x DCLK
4 x DCLK
GRUNDIG Service
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