Standard Event Status Register ( Esr); Standard Event Status Enable Register ( Ese ) - COSINUS ESCORT 3145A Bedienungsanleitung

ESCORT 3145A / 3146A

7.4.8 Standard Event Status Register ( ESR)

Bit7 Bit6
PON 0
Bit 0 (OPC) - Operation complete. This bit is generated in response to the
Bit 1 is not used. (Always set to 0 )
Bit 2 (QYE) - Query Error. Attempt has been made to read the Output Queue
Bit 3 (DDE) - Device-Dependent Error. Incorrect input during calibration, or
Bit 4 (EXE) - Execution Error. Execution Error will occur beside no command
Bit 5 (CME) - Command Error. Command or parameter is wrong or unknown.
Bit 6 is not used. (Always set to 0)
Bit 7 (PON) - Power On. Power has been cycled off and on since the last
Note: 1. The Standard Event Status Register can be read by the *ESR?
query.
2. The register is cleared at power up or use *ESR? and *CLS commands.

7.4.9 Standard Event Status Enable Register ( ESE )

The Standard Event Status Enable Register is a mask register that allows the
host to enable or disable (mask) each bit in ESR. When a bit in the ESE is 1,
the corresponding bit in the ESR is enable. When any enabled bit in the ESR
changes from 0 to 1, the ESB summary bit (bit 5) of the STB register also
goes to 1.
Use *ESE to write to this register and *ESE? to read this register.
Figure 7-1 shows all status system register groups and queues in the
meter.
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Bit5 Bit4
CME EXE
*OPC command and indicates that the interface is ready to
accept another message.
when no output is present or pending. Or, both input and output
buffer are full.
RS-232 input buffer overflow.
error but it is happened as following example, to query compare
result, but instrument has not been set in compare mode.
time the ESR was read.
Bit3 Bit2
DDE QYE
Seite 7-87
Bit1 Bit0
0 OPC