Video/Deflection Controller Tda9332 (Deflection Area); Clock Generation/Phase 2 Loop; Dac For Ow/V Control; Beam Current Dependent Correction - Loewe Q2500B Serviceanleitung

Technology of Q 2500 colour TV set
With this module the PIP function can be used
with our devices. Split screen and Multi PIP
are not used.
This processor does not form part of the digi-
tal signal processing. As you can see from the
circuit diagram, the RGB signals from SDA
9488 pins 15/16 and 17 are fed directly to
TDA 9332 (pins 30/31/32).
SDA 9488 receives the FBAS or Y/C signal to
be processed on pins 26/28 from the video-
conversion IC.
The necessary 100 Hz V/H synchronous sig-
nals are fed to pins 4 and 3.
For our medium devices as for our high vari-
ant a VGA interface can be retro-fitted. The
VGA RGB signals are not, however, fed di-
rectly into the TDA 9332, as in the high-end
device, but for VGA operation are looped
through the SDA 9488 to the TDA 9332.
From the VGA interface the RGB signals are
led to pins 11/12 and 13 of SDA 9488.
4.9 Video/deflection controller
TDA9332
The Philips TDA 9332 video/deflection control-
ler can be used in standard TV's as well as in
devices with double picture and line fre-
quency.
The video/deflection controller is switched in
the Q 2500 chassis in such a way that it can
drive the H/V deflection with double the fre-
quency.

4.9.1 Clock generation/Phase 2 loop

All the necessary cycle and synchronous sig-
nals necessary for internal signal processing
are derived from this block.
The synchronous signals generated by SAA
4979 are fed to pin 24 (H synchronous signal)
and to pin 23 (V synchronous signal) of the
controller. The cycle frequency for the video/
deflection processor is produced with an ex-
ternal 12 MHz quartz on pins 20 and 21. This
cycle is synchronised by a PLL that operates
with the horizontal synchronous pulse HA.
Document Q 2500
(deflection area)

4.9.2 DAC for OW/V control

and H output stage
The DACs for the two vertical -VD+ control
signals contain all vertical correction informa-
tion. The VD+ control signals are output to
pins 1/2 and are fed via R 1032 and R 1033 to
pins 2/3 of W 1511. In this way the V output
stage on the basic board is controlled by d.c.
The vertical frequency E/W parabola also con-
tains all correction information. The control
signal is output by I 2521 on pin 3 and is fed
via W 1511 pin 6 to the basic board. In this
way the E/W output stage on the basic board
is controlled.
The horizontal output is programmed in such
a way that on pin 8 a rectangular signal with
13 µs H and 19 µs L level for control of the H-
output stage on the basic board is output. The
signal reaches Q 2556 and Q 2561 on pin 13
of pin connector W 1511 via two inverter
stages and controls H output stage Q 534 on
the basic board via H driver stage Q 526.
In the SAT standby, for SAT radio and for
overwriting in standby, the c.r.t. must be
switched off. For this the horizontal pulse is
switched off via transistor Q 2951. The control
of Q 2951 is implemented via pin 79 of the
SDA 6000 microprocessor. The c.r.t. is
switched off here with H level.

4.9.3 Beam current dependent correction

the vertical/horizontal
amplitude and the H phase
As we know the high voltage at the anode
connection of the c.r.t diminishes at high
beam currents, owing to the internal resis-
tance of the high voltage generation. The
lower high voltage means that the beam of
electrons is not so strongly accelerated and
can be deflected outwards again by the V/H
magnetic deflection fields. The picture be-
comes larger.
If the beam current decreases (darker picture
content) the picture becomes smaller again.
Appropriate corrective measures are neces-
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