Loewe Q2500B Serviceanleitung Seite 197

Technology of Q 2500 colour TV set
The end of data transfer (Stop condition) oc-
curs on signalisation of a positive flank (L > H)
on the DATA line and concurrent H level on
the clock line.
SDA
SCL
Master-
Slave-
Sender/
Receiver
Receiver
Receiver
(µC) (Display) (RAM)
Start
SCL from
master
SDA signal
via transmitter
SDA signal
S
via receiver
Up to 400 kbit/s can be transferred via the I²C
bus interface of the SDA 6000. The data and
clock impulses are switched by software
switching logic to the respectively required
bus connections.
The CCU operates on its I2C bus outputs with
a level of 3.3 V. The other ICs and compo-
nents operate with TTL level. Adaptation of
the CCU level to the TTL level is by transistors
Q 2883/86/88/91 and Q 2893.
The following functions are controlled via the
I²C bus systems:
I²C bus 0 with SDA 0 and SCL 0
Only the EAROM I 2931 is connected to the
I²C bus 0. This memory contains all start val-
ues and customer specific values. The data is
selected here on start up and when making
adjustments or writing to the EAROM on shut
down and for memory processes.
If a DVB module is retro-fitted the second
EAROM I 2936 is also used. Programme data
from 220 to 1470 is stored here.
Document Q 2500
Slave- Slave-
Master-
Sender/
Sender/
Sender
Receiver
(µC) (E/A-Interface)
9th clock bit for A
1 2 8 9
• Multi-sound processor MSP 3410 to IF-
and VF processing.
•
The video processor VPC 3230, I 2271 for
digitising of input signals and processing in
the main signal path. It conducts the digital
Y/UV signals to the I 491 memory.
• SAA 4979 for conversion of the digital Y
and C signals into analogue Y, R-Y and B-
Y signals and for the control of the digital
100 Hz processing with the two half picture
memories and the SAA 4993.
• The video/deflection processor TDA 9332
for generation of the RGB control signals
for the c.r.t. plate and for generation of the
deflection pulse
• Video processor VPC 3233, I 2151 for PIP
signal processing. The digitised Y/UV-
signals are fed to the two PIP synchronous
memories I 2161/71.
The I²C bus has a maximum cycle rate of 400
kHz.
I²C bus 1 with SDA 1 and SCL 1
Just like the I²C bus 0, fixed pins are also pro-
vided for the I²C buses 1 and 2 in the SDA
6000. Buses 1 and 2 operate with a common
clock line and separate data lines. Data is
switched to the respective line for the required
bus in an internal transfer switch.
The following are connect to the I²C bus 1:
• The tuning and transfer IC's on the receiver
units in the basic board.
• The transfer IC's for video (1 x TEA 6415)
and audio (TEA 6422 and TEA 6420) for
the interface on the signal board.
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