Microprocessor Interface; Control Of The 100 Hz Processing; Video/Deflection Processor Tda 9332/Range Video/Rgb Path - Loewe Q2500B Serviceanleitung

Technology of Q 2500 colour TV set
Via the sampling circuit, the digital Y signal,
which is now 9-bits wide, reaches a DAC,
which generates an analogue signal. This is
then output on pin 44 at 1.5 Vss.
4.6.5

Microprocessor interface

All processes in the SAA 4979 are controlled
by SDA6000 via the I²C bus 0 (pin 1 = SDA,
pin 2 = SCL). In addition, information for the
SAA 4993 and the memory control is also
transferred.
The SAA 4993 is controlled by the BESIC via
the microprocessor bus to pins 108 (µP DA)
and 107 (µP CL).
Switching outputs 4 are used for the switching
of the VGA synchronisation. If a switch is
made to the VGA programme location, then
pin 4 is switched from I 2311 to L level. With
this logic state the vertical synchronous pulse
of the VGA interface W 1011 pin 4 is switched
directly to the video/deflector controller I 2521
via the four Nand gates I 2361 A/B/C and D.
The VGA synchronous pulse is, in addition,
monitored by I 2271 on its pin 17. If no syn-
chronisation or false synchronisation is de-
tected, I 2311 resets its output on pin 4 and
thereby switches over to internal V synchroni-
sation.

4.6.6 Control of the 100 Hz processing

(Display)
This stage synchronises the read out from the
half pictures and the writing to memory in the
second memory. As the signals in the SAA
4993 are written to and read out, it has direct
control and is only synchronised by the
BESIC.
Via pulse RE (pin 84) the Falconic module
controls the reading from both half picture
memories and the writing to the second mem-
ory.
With pulse IE (pin 83) SAA 4979 controls the
data inputs in the second half picture memory.
With L level a switch can be made to freeze
frame, for example.
Document Q 2500
Furthermore, the display stage gives a hori-
zontal pulse on pin 54 and a vertical synchro-
nous pulse on pin 55 for the synchronisation
of the deflection in TDA9332. At the same
time, the vertical pulse VD acts as a reset for
the Falconic and the half picture memories, for
resetting the address counter on reading from
the memory and for writing to the second
memory.
4.7 Video/deflection processor TDA
9332/Range Video/RGB path
The last IC for picture signal processing, apart
from the RGB output stages, is the TDA 9332.
It also controls the deflection stage.
Inputs for analogue R-Y, B-Y and Y signals:
- Two RGB inputs for analogue signals from
the CCU and the VGA interface and/or pic-
ture in picture generation
- Matrix circuits for RGB generation from the
difference signals
- Signal selection for the switching of the
required RGB signals
- Y and colour difference matrix for the gen-
eration of Y and difference signals from the
selected RGB signal
- Hue control for NTSC operation and
gamma correction in the Y branch
- Saturation, contrast and brightness setting
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