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Output Format Conversion; Synchronisation Block; I²C Bus Interface; Half Picture Memory Saa4955Hl - Loewe Q2500B Serviceanleitung

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Technology of Q 2500 colour TV set
Zoom
Cinema
Panorama
4 : 3
0
14
20
As 4:3 picture presentation with upper and
lower black areas can lead to false results, the
analysis occurs 4 sec. before switching oc-
curs. If, however, undesired conversion proc-
esses occur, the function can be switched off
with the remote control.

4.3.6 Output format conversion

Up to now luminance and chroma signals
have been processed IC internally at a cycle
rate of 20.25 MHz. For additional processing
by the 100 Hz Philips IC set, an output cycle
rate of 13.5 MHz is required. In the Output
Formatter, therefore, the output data is con-
verted from 20.25 MHz to 13.5 MHz. The YUV
output format is also converted at this stage to
4:2:2 and output by a multiplex procedure to 8
lines. The multiplex cycle rate must therefore
have the double cycle rate of 13.5 MHz. The
multiple cycle rate on pin 27 of I 2271/ there-
fore has a frequency of 27 MHz.
4.3.7

Synchronisation block

The synchronisation block generates all the
synchronous, sampling, cycle and clamp sig-
nals that are necessary for internal and exter-
nal signal processing.
Before the digital video signal reaches the
horizontal and vertical synchronous separa-
tion stage, it passes through a 1 MHz low-
pass. With the low-pass, video and noise
components >1 MHz are suppressed. All sig-
nals that are required for the various process-
Document Q 2500
28
34
40
Number of lines
in lower and upper area
Luminance /Chroma <10%
ing steps in the VPC are controlled via an in-
ternal PLL stage and counter.
No special synchronous signals are used for
other
external
SAA4979 detects picture and line start from
the data delivered by the VPC, and for further
signal processing produces independent V/H
synchronous signals. The VPC 3230 supplies
the 27 MHz multiplex cycle to pin 27 for the
digital luminance/chroma signals.
4.3.8 I²C bus interface
Communication between C 161 and VPCm is
via the I²C bus interface. The register in the
VPC is loaded via this interface after start up
and the status in operation is selected via it.

4.4 Half picture memory SAA4955HL

The two memory IC's and the memory inte-
grated into the SAA 4979 are functionally
identical, their tasks , however, are different.
90
signal
processing.
© Loewe ProCollege
The

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