Advanced Chipset Features - Kontron Embedded Computers Inline-P3 E Benutzerhandbuch

Phoenix- Award BIOS Configuration

Advanced Chipset Features

This section allows you to configure the system based on the specific features of
the installed chipset. This chipset controls bus speeds and access to system
memory resources, such as DRAM and the external cache. It also coordinates
communications between the conventional ISA bus and the PCI bus.
DRAM Timing By SPD
DRAM Clock
RAM Cycle Length
Bank Interleave
Memory Hole
P2C/C2P Concurrency
System BIOS Cacheable
Frame Buffer Size
AGP Aperture Size
AGP – 4x Mode
USB Port1 & Port2
USB Port3 & Port4
USB Keyboard Support
Onchip Sound
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master WS Read
Options:
DRAM Timing By SPD
DRAM Clock
SDRAM Cycle length
Bank Interleave
Memory Hole
P2C/C2P Concurrency
System BIOS Cachable
Video RMA Cachable
Frame Buffer Size
56
Phoenix AwardBIOS CMOS Setup Utility
Advanced Chipset Features
: Enabled
: Host CLK
: 3
: Disabled
: Disabled
: Enabled
: Enabled
: 16M
: 64M
: Enabled
: Enabled
: Disabled
: Enabled
: Disabled
: Enabled
: Enabled
: Enabled
: Enabled
: Enabled
: Disabled
Disabled -Enabled
Host CLK -HCLK -33M-HCLK +33M
3 - 2
Disable - 2 Bank - 4 Bank
Disable - 15M - 16M
Disabled - Enabled
Disabled - Enabled
Disabled - Enabled
2M - 4M - 8M - 16M - 32M
Item help
Menu Level >
INLine-P3_e – Benutzerhandbuch