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9.35
PCI Express Root Port X
Bios-Eintrag
PCI Express Root Port 1
Topolgy
ASPM
L1 Substates
Gen3 Eq Phase3 Method
UDTP
DPTP
ACS
URR
FER
NFER
CER
CTO
SEFE
SENFE
SECE
PME SCI
Hot Plug
Advanced Error Reporting
PCIe Speed
Transmitter Half Swing
Detect Timeout
Extra Bus Reserved
Reserved I/O
PCH PCIe LTR Configuration
PCH PCIE1 LTR
Snoop Latency Override
Snoop Latency Value
Snoop Latency Multipler
Non Snoop Latency Override
CB6464
Optionen
Disabled / Enabled
Unknown / x1 / x4 / Sata Express / M2
L0sL1 / L1 L0s / Disabled / Auto
Disabled / L1.1 & L1.2 / L1.1 / L1.2
Hardware / Static Coeff. / Software Search
0..10
0..10
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Disabled / Enabled
Auto / Gen1 / Gen2 / Gen3
Disabled / Enabled
0..65535
0..7
4K / 8K / 12K / 16K / 20K
Disabled / Enabled
Disabled / Manual / Auto
0..1023
1 ns / 32 ns / 1024 ns / 32768 ns / 1048576 ns / 33554432 ns
Disabled / Manual / Auto
Version: 0.3
BIOS
57
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